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[TTI] Use TypeSize in isLoadFromStackSlot and isStoreToStackSlot [nfc] (#132244)
Motivation is supporting scalable spills and reloads, e.g. in #120524. Looking at this API, I'm suspicious that the access size should just be coming from the memory operand on the load or store, but we don't appear to be consistently setting that up. That's a larger change so I may or may not bother pursuing that.
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6 files changed

+45
-44
lines changed

6 files changed

+45
-44
lines changed

‎llvm/include/llvm/CodeGen/TargetInstrInfo.h

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@
3131
#include "llvm/MC/MCInstrInfo.h"
3232
#include "llvm/Support/BranchProbability.h"
3333
#include "llvm/Support/ErrorHandling.h"
34+
#include "llvm/Support/TypeSize.h"
3435
#include <array>
3536
#include <cassert>
3637
#include <cstddef>
@@ -293,8 +294,8 @@ class TargetInstrInfo : public MCInstrInfo {
293294
/// what the load does.
294295
virtual Register isLoadFromStackSlot(const MachineInstr &MI,
295296
int &FrameIndex,
296-
unsigned &MemBytes) const {
297-
MemBytes = 0;
297+
TypeSize &MemBytes) const {
298+
MemBytes = TypeSize::getZero();
298299
return isLoadFromStackSlot(MI, FrameIndex);
299300
}
300301

@@ -331,8 +332,8 @@ class TargetInstrInfo : public MCInstrInfo {
331332
/// what the store does.
332333
virtual Register isStoreToStackSlot(const MachineInstr &MI,
333334
int &FrameIndex,
334-
unsigned &MemBytes) const {
335-
MemBytes = 0;
335+
TypeSize &MemBytes) const {
336+
MemBytes = TypeSize::getZero();
336337
return isStoreToStackSlot(MI, FrameIndex);
337338
}
338339

‎llvm/lib/CodeGen/StackSlotColoring.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -484,8 +484,8 @@ bool StackSlotColoring::RemoveDeadStores(MachineBasicBlock* MBB) {
484484

485485
Register LoadReg;
486486
Register StoreReg;
487-
unsigned LoadSize = 0;
488-
unsigned StoreSize = 0;
487+
TypeSize LoadSize = TypeSize::getZero();
488+
TypeSize StoreSize = TypeSize::getZero();
489489
if (!(LoadReg = TII->isLoadFromStackSlot(*I, FirstSS, LoadSize)))
490490
continue;
491491
// Skip the ...pseudo debugging... instructions between a load and store.

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -95,35 +95,35 @@ MCInst RISCVInstrInfo::getNop() const {
9595

9696
Register RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
9797
int &FrameIndex) const {
98-
unsigned Dummy;
98+
TypeSize Dummy = TypeSize::getZero();
9999
return isLoadFromStackSlot(MI, FrameIndex, Dummy);
100100
}
101101

102102
Register RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
103103
int &FrameIndex,
104-
unsigned &MemBytes) const {
104+
TypeSize &MemBytes) const {
105105
switch (MI.getOpcode()) {
106106
default:
107107
return 0;
108108
case RISCV::LB:
109109
case RISCV::LBU:
110-
MemBytes = 1;
110+
MemBytes = TypeSize::getFixed(1);
111111
break;
112112
case RISCV::LH:
113113
case RISCV::LH_INX:
114114
case RISCV::LHU:
115115
case RISCV::FLH:
116-
MemBytes = 2;
116+
MemBytes = TypeSize::getFixed(2);
117117
break;
118118
case RISCV::LW:
119119
case RISCV::LW_INX:
120120
case RISCV::FLW:
121121
case RISCV::LWU:
122-
MemBytes = 4;
122+
MemBytes = TypeSize::getFixed(4);
123123
break;
124124
case RISCV::LD:
125125
case RISCV::FLD:
126-
MemBytes = 8;
126+
MemBytes = TypeSize::getFixed(8);
127127
break;
128128
}
129129

@@ -138,32 +138,32 @@ Register RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
138138

139139
Register RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
140140
int &FrameIndex) const {
141-
unsigned Dummy;
141+
TypeSize Dummy = TypeSize::getZero();
142142
return isStoreToStackSlot(MI, FrameIndex, Dummy);
143143
}
144144

145145
Register RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
146146
int &FrameIndex,
147-
unsigned &MemBytes) const {
147+
TypeSize &MemBytes) const {
148148
switch (MI.getOpcode()) {
149149
default:
150150
return 0;
151151
case RISCV::SB:
152-
MemBytes = 1;
152+
MemBytes = TypeSize::getFixed(1);
153153
break;
154154
case RISCV::SH:
155155
case RISCV::SH_INX:
156156
case RISCV::FSH:
157-
MemBytes = 2;
157+
MemBytes = TypeSize::getFixed(2);
158158
break;
159159
case RISCV::SW:
160160
case RISCV::SW_INX:
161161
case RISCV::FSW:
162-
MemBytes = 4;
162+
MemBytes = TypeSize::getFixed(4);
163163
break;
164164
case RISCV::SD:
165165
case RISCV::FSD:
166-
MemBytes = 8;
166+
MemBytes = TypeSize::getFixed(8);
167167
break;
168168
}
169169

‎llvm/lib/Target/RISCV/RISCVInstrInfo.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -70,11 +70,11 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
7070
Register isLoadFromStackSlot(const MachineInstr &MI,
7171
int &FrameIndex) const override;
7272
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex,
73-
unsigned &MemBytes) const override;
73+
TypeSize &MemBytes) const override;
7474
Register isStoreToStackSlot(const MachineInstr &MI,
7575
int &FrameIndex) const override;
7676
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex,
77-
unsigned &MemBytes) const override;
77+
TypeSize &MemBytes) const override;
7878

7979
bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
8080

‎llvm/lib/Target/X86/X86InstrInfo.cpp

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -486,21 +486,21 @@ bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
486486
return false;
487487
}
488488

489-
static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
489+
static bool isFrameLoadOpcode(int Opcode, TypeSize &MemBytes) {
490490
switch (Opcode) {
491491
default:
492492
return false;
493493
case X86::MOV8rm:
494494
case X86::KMOVBkm:
495495
case X86::KMOVBkm_EVEX:
496-
MemBytes = 1;
496+
MemBytes = TypeSize::getFixed(1);
497497
return true;
498498
case X86::MOV16rm:
499499
case X86::KMOVWkm:
500500
case X86::KMOVWkm_EVEX:
501501
case X86::VMOVSHZrm:
502502
case X86::VMOVSHZrm_alt:
503-
MemBytes = 2;
503+
MemBytes = TypeSize::getFixed(2);
504504
return true;
505505
case X86::MOV32rm:
506506
case X86::MOVSSrm:
@@ -511,7 +511,7 @@ static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
511511
case X86::VMOVSSZrm_alt:
512512
case X86::KMOVDkm:
513513
case X86::KMOVDkm_EVEX:
514-
MemBytes = 4;
514+
MemBytes = TypeSize::getFixed(4);
515515
return true;
516516
case X86::MOV64rm:
517517
case X86::LD_Fp64m:
@@ -525,7 +525,7 @@ static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
525525
case X86::MMX_MOVQ64rm:
526526
case X86::KMOVQkm:
527527
case X86::KMOVQkm_EVEX:
528-
MemBytes = 8;
528+
MemBytes = TypeSize::getFixed(8);
529529
return true;
530530
case X86::MOVAPSrm:
531531
case X86::MOVUPSrm:
@@ -551,7 +551,7 @@ static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
551551
case X86::VMOVDQU32Z128rm:
552552
case X86::VMOVDQA64Z128rm:
553553
case X86::VMOVDQU64Z128rm:
554-
MemBytes = 16;
554+
MemBytes = TypeSize::getFixed(16);
555555
return true;
556556
case X86::VMOVAPSYrm:
557557
case X86::VMOVUPSYrm:
@@ -571,7 +571,7 @@ static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
571571
case X86::VMOVDQU32Z256rm:
572572
case X86::VMOVDQA64Z256rm:
573573
case X86::VMOVDQU64Z256rm:
574-
MemBytes = 32;
574+
MemBytes = TypeSize::getFixed(32);
575575
return true;
576576
case X86::VMOVAPSZrm:
577577
case X86::VMOVUPSZrm:
@@ -583,33 +583,33 @@ static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
583583
case X86::VMOVDQU32Zrm:
584584
case X86::VMOVDQA64Zrm:
585585
case X86::VMOVDQU64Zrm:
586-
MemBytes = 64;
586+
MemBytes = TypeSize::getFixed(64);
587587
return true;
588588
}
589589
}
590590

591-
static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
591+
static bool isFrameStoreOpcode(int Opcode, TypeSize &MemBytes) {
592592
switch (Opcode) {
593593
default:
594594
return false;
595595
case X86::MOV8mr:
596596
case X86::KMOVBmk:
597597
case X86::KMOVBmk_EVEX:
598-
MemBytes = 1;
598+
MemBytes = TypeSize::getFixed(1);
599599
return true;
600600
case X86::MOV16mr:
601601
case X86::KMOVWmk:
602602
case X86::KMOVWmk_EVEX:
603603
case X86::VMOVSHZmr:
604-
MemBytes = 2;
604+
MemBytes = TypeSize::getFixed(2);
605605
return true;
606606
case X86::MOV32mr:
607607
case X86::MOVSSmr:
608608
case X86::VMOVSSmr:
609609
case X86::VMOVSSZmr:
610610
case X86::KMOVDmk:
611611
case X86::KMOVDmk_EVEX:
612-
MemBytes = 4;
612+
MemBytes = TypeSize::getFixed(4);
613613
return true;
614614
case X86::MOV64mr:
615615
case X86::ST_FpP64m:
@@ -621,7 +621,7 @@ static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
621621
case X86::MMX_MOVNTQmr:
622622
case X86::KMOVQmk:
623623
case X86::KMOVQmk_EVEX:
624-
MemBytes = 8;
624+
MemBytes = TypeSize::getFixed(8);
625625
return true;
626626
case X86::MOVAPSmr:
627627
case X86::MOVUPSmr:
@@ -647,7 +647,7 @@ static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
647647
case X86::VMOVDQU64Z128mr:
648648
case X86::VMOVDQU8Z128mr:
649649
case X86::VMOVDQU16Z128mr:
650-
MemBytes = 16;
650+
MemBytes = TypeSize::getFixed(16);
651651
return true;
652652
case X86::VMOVUPSYmr:
653653
case X86::VMOVAPSYmr:
@@ -667,7 +667,7 @@ static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
667667
case X86::VMOVDQU32Z256mr:
668668
case X86::VMOVDQA64Z256mr:
669669
case X86::VMOVDQU64Z256mr:
670-
MemBytes = 32;
670+
MemBytes = TypeSize::getFixed(32);
671671
return true;
672672
case X86::VMOVUPSZmr:
673673
case X86::VMOVAPSZmr:
@@ -679,21 +679,21 @@ static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
679679
case X86::VMOVDQU32Zmr:
680680
case X86::VMOVDQA64Zmr:
681681
case X86::VMOVDQU64Zmr:
682-
MemBytes = 64;
682+
MemBytes = TypeSize::getFixed(64);
683683
return true;
684684
}
685685
return false;
686686
}
687687

688688
Register X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
689689
int &FrameIndex) const {
690-
unsigned Dummy;
690+
TypeSize Dummy = TypeSize::getZero();
691691
return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, Dummy);
692692
}
693693

694694
Register X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
695695
int &FrameIndex,
696-
unsigned &MemBytes) const {
696+
TypeSize &MemBytes) const {
697697
if (isFrameLoadOpcode(MI.getOpcode(), MemBytes))
698698
if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
699699
return MI.getOperand(0).getReg();
@@ -702,7 +702,7 @@ Register X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
702702

703703
Register X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
704704
int &FrameIndex) const {
705-
unsigned Dummy;
705+
TypeSize Dummy = TypeSize::getZero();
706706
if (isFrameLoadOpcode(MI.getOpcode(), Dummy)) {
707707
if (Register Reg = isLoadFromStackSlot(MI, FrameIndex))
708708
return Reg;
@@ -720,13 +720,13 @@ Register X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
720720

721721
Register X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
722722
int &FrameIndex) const {
723-
unsigned Dummy;
723+
TypeSize Dummy = TypeSize::getZero();
724724
return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, Dummy);
725725
}
726726

727727
Register X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
728728
int &FrameIndex,
729-
unsigned &MemBytes) const {
729+
TypeSize &MemBytes) const {
730730
if (isFrameStoreOpcode(MI.getOpcode(), MemBytes))
731731
if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
732732
isFrameOperand(MI, 0, FrameIndex))
@@ -736,7 +736,7 @@ Register X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
736736

737737
Register X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
738738
int &FrameIndex) const {
739-
unsigned Dummy;
739+
TypeSize Dummy = TypeSize::getZero();
740740
if (isFrameStoreOpcode(MI.getOpcode(), Dummy)) {
741741
if (Register Reg = isStoreToStackSlot(MI, FrameIndex))
742742
return Reg;

‎llvm/lib/Target/X86/X86InstrInfo.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -276,7 +276,7 @@ class X86InstrInfo final : public X86GenInstrInfo {
276276
int &FrameIndex) const override;
277277
Register isLoadFromStackSlot(const MachineInstr &MI,
278278
int &FrameIndex,
279-
unsigned &MemBytes) const override;
279+
TypeSize &MemBytes) const override;
280280
/// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
281281
/// stack locations as well. This uses a heuristic so it isn't
282282
/// reliable for correctness.
@@ -287,7 +287,7 @@ class X86InstrInfo final : public X86GenInstrInfo {
287287
int &FrameIndex) const override;
288288
Register isStoreToStackSlot(const MachineInstr &MI,
289289
int &FrameIndex,
290-
unsigned &MemBytes) const override;
290+
TypeSize &MemBytes) const override;
291291
/// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
292292
/// stack locations as well. This uses a heuristic so it isn't
293293
/// reliable for correctness.

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