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Chen Zheng
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[PowerPC] Make StartMI ignore COPY like instructions.
Reviewed By: lkail Differential Revision: https://reviews.llvm.org/D85659
1 parent aa61e43 commit 4d52ebb

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3 files changed

+52
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3 files changed

+52
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llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

Lines changed: 31 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -2655,22 +2655,35 @@ const unsigned *PPCInstrInfo::getLoadOpcodesForSpillArray() const {
26552655
return LoadSpillOpcodesArray[getSpillTarget()];
26562656
}
26572657

2658-
void PPCInstrInfo::fixupIsDeadOrKill(MachineInstr &StartMI, MachineInstr &EndMI,
2658+
void PPCInstrInfo::fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI,
26592659
unsigned RegNo) const {
26602660
// Conservatively clear kill flag for the register if the instructions are in
26612661
// different basic blocks and in SSA form, because the kill flag may no longer
26622662
// be right. There is no need to bother with dead flags since defs with no
26632663
// uses will be handled by DCE.
2664-
MachineRegisterInfo &MRI = StartMI.getParent()->getParent()->getRegInfo();
2665-
if (MRI.isSSA() && (StartMI.getParent() != EndMI.getParent())) {
2664+
MachineRegisterInfo &MRI = StartMI->getParent()->getParent()->getRegInfo();
2665+
if (MRI.isSSA() && (StartMI->getParent() != EndMI->getParent())) {
26662666
MRI.clearKillFlags(RegNo);
26672667
return;
26682668
}
26692669

26702670
// Instructions between [StartMI, EndMI] should be in same basic block.
2671-
assert((StartMI.getParent() == EndMI.getParent()) &&
2671+
assert((StartMI->getParent() == EndMI->getParent()) &&
26722672
"Instructions are not in same basic block");
26732673

2674+
// If before RA, StartMI may be def through COPY, we need to adjust it to the
2675+
// real def. See function getForwardingDefMI.
2676+
if (MRI.isSSA()) {
2677+
bool Reads, Writes;
2678+
std::tie(Reads, Writes) = StartMI->readsWritesVirtualRegister(RegNo);
2679+
if (!Reads && !Writes) {
2680+
assert(Register::isVirtualRegister(RegNo) &&
2681+
"Must be a virtual register");
2682+
// Get real def and ignore copies.
2683+
StartMI = MRI.getVRegDef(RegNo);
2684+
}
2685+
}
2686+
26742687
bool IsKillSet = false;
26752688

26762689
auto clearOperandKillInfo = [=] (MachineInstr &MI, unsigned Index) {
@@ -2683,21 +2696,21 @@ void PPCInstrInfo::fixupIsDeadOrKill(MachineInstr &StartMI, MachineInstr &EndMI,
26832696
// Set killed flag for EndMI.
26842697
// No need to do anything if EndMI defines RegNo.
26852698
int UseIndex =
2686-
EndMI.findRegisterUseOperandIdx(RegNo, false, &getRegisterInfo());
2699+
EndMI->findRegisterUseOperandIdx(RegNo, false, &getRegisterInfo());
26872700
if (UseIndex != -1) {
2688-
EndMI.getOperand(UseIndex).setIsKill(true);
2701+
EndMI->getOperand(UseIndex).setIsKill(true);
26892702
IsKillSet = true;
26902703
// Clear killed flag for other EndMI operands related to RegNo. In some
26912704
// upexpected cases, killed may be set multiple times for same register
26922705
// operand in same MI.
2693-
for (int i = 0, e = EndMI.getNumOperands(); i != e; ++i)
2706+
for (int i = 0, e = EndMI->getNumOperands(); i != e; ++i)
26942707
if (i != UseIndex)
2695-
clearOperandKillInfo(EndMI, i);
2708+
clearOperandKillInfo(*EndMI, i);
26962709
}
26972710

26982711
// Walking the inst in reverse order (EndMI -> StartMI].
2699-
MachineBasicBlock::reverse_iterator It = EndMI;
2700-
MachineBasicBlock::reverse_iterator E = EndMI.getParent()->rend();
2712+
MachineBasicBlock::reverse_iterator It = *EndMI;
2713+
MachineBasicBlock::reverse_iterator E = EndMI->getParent()->rend();
27012714
// EndMI has been handled above, skip it here.
27022715
It++;
27032716
MachineOperand *MO = nullptr;
@@ -2723,13 +2736,13 @@ void PPCInstrInfo::fixupIsDeadOrKill(MachineInstr &StartMI, MachineInstr &EndMI,
27232736
} else if ((MO = It->findRegisterDefOperand(RegNo, false, true,
27242737
&getRegisterInfo()))) {
27252738
// No use found, set dead for its def.
2726-
assert(&*It == &StartMI && "No new def between StartMI and EndMI.");
2739+
assert(&*It == StartMI && "No new def between StartMI and EndMI.");
27272740
MO->setIsDead(true);
27282741
break;
27292742
}
27302743
}
27312744

2732-
if ((&*It) == &StartMI)
2745+
if ((&*It) == StartMI)
27332746
break;
27342747
}
27352748
// Ensure RegMo liveness is killed after EndMI.
@@ -3860,7 +3873,7 @@ bool PPCInstrInfo::simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
38603873
// ForwardingOperandReg = LI imm1
38613874
// y = op2 imm2, ForwardingOperandReg(killed)
38623875
if (IsForwardingOperandKilled)
3863-
fixupIsDeadOrKill(DefMI, MI, ForwardingOperandReg);
3876+
fixupIsDeadOrKill(&DefMI, &MI, ForwardingOperandReg);
38643877

38653878
LLVM_DEBUG(dbgs() << "With:\n");
38663879
LLVM_DEBUG(MI.dump());
@@ -3952,9 +3965,9 @@ bool PPCInstrInfo::transformToNewImmFormFedByAdd(
39523965

39533966
// Update kill flag
39543967
if (RegMO->isKill() || IsKilledFor(RegMO->getReg()))
3955-
fixupIsDeadOrKill(DefMI, MI, RegMO->getReg());
3968+
fixupIsDeadOrKill(&DefMI, &MI, RegMO->getReg());
39563969
if (ForwardKilledOperandReg != ~0U)
3957-
fixupIsDeadOrKill(DefMI, MI, ForwardKilledOperandReg);
3970+
fixupIsDeadOrKill(&DefMI, &MI, ForwardKilledOperandReg);
39583971
}
39593972

39603973
LLVM_DEBUG(dbgs() << "With:\n");
@@ -4065,12 +4078,12 @@ bool PPCInstrInfo::transformToImmFormFedByAdd(
40654078
// x = ADD reg(killed), imm
40664079
// y = XOP 0, x
40674080
if (IsFwdFeederRegKilled || RegMO->isKill())
4068-
fixupIsDeadOrKill(DefMI, MI, RegMO->getReg());
4081+
fixupIsDeadOrKill(&DefMI, &MI, RegMO->getReg());
40694082
// Pattern 3:
40704083
// ForwardKilledOperandReg = ADD reg, imm
40714084
// y = XOP 0, ForwardKilledOperandReg(killed)
40724085
if (ForwardKilledOperandReg != ~0U)
4073-
fixupIsDeadOrKill(DefMI, MI, ForwardKilledOperandReg);
4086+
fixupIsDeadOrKill(&DefMI, &MI, ForwardKilledOperandReg);
40744087

40754088
LLVM_DEBUG(dbgs() << "With:\n");
40764089
LLVM_DEBUG(MI.dump());
@@ -4226,7 +4239,7 @@ bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI,
42264239
// ForwardKilledOperandReg = LI imm
42274240
// y = XOP reg, ForwardKilledOperandReg(killed)
42284241
if (ForwardKilledOperandReg != ~0U)
4229-
fixupIsDeadOrKill(DefMI, MI, ForwardKilledOperandReg);
4242+
fixupIsDeadOrKill(&DefMI, &MI, ForwardKilledOperandReg);
42304243
return true;
42314244
}
42324245

llvm/lib/Target/PowerPC/PPCInstrInfo.h

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -567,14 +567,16 @@ class PPCInstrInfo : public PPCGenInstrInfo {
567567
/// up. Before calling this function,
568568
/// 1. Ensure that \p RegNo liveness is killed after instruction \p EndMI.
569569
/// 2. Ensure that there is no new definition between (\p StartMI, \p EndMI)
570-
/// and possible definition for \p RegNo is \p StartMI or \p EndMI.
570+
/// and possible definition for \p RegNo is \p StartMI or \p EndMI. For
571+
/// pre-RA cases, definition may be \p StartMI through COPY, \p StartMI
572+
/// will be adjust to true definition.
571573
/// 3. We can do accurate fixup for the case when all instructions between
572574
/// [\p StartMI, \p EndMI] are in same basic block.
573575
/// 4. For the case when \p StartMI and \p EndMI are not in same basic block,
574576
/// we conservatively clear kill flag for all uses of \p RegNo for pre-RA
575577
/// and for post-RA, we give an assertion as without reaching definition
576578
/// analysis post-RA, \p StartMI and \p EndMI are hard to keep right.
577-
void fixupIsDeadOrKill(MachineInstr &StartMI, MachineInstr &EndMI,
579+
void fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI,
578580
unsigned RegNo) const;
579581
void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const;
580582
void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo,

llvm/test/CodeGen/PowerPC/fixup-kill-dead-flag-crash.mir

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,3 +19,20 @@ body: |
1919
STW killed %4:gprc, %4:gprc, 100
2020
BLR8 implicit $lr8, implicit $rm
2121
...
22+
---
23+
name: test2
24+
#CHECK : name : test2
25+
tracksRegLiveness: true
26+
body: |
27+
bb.0.entry:
28+
liveins: $r3
29+
%0:gprc = COPY $r3
30+
%1:gprc_and_gprc_nor0 = LI 0
31+
; CHECK: dead %2:gprc = COPY %1
32+
%2:gprc = COPY %1:gprc_and_gprc_nor0
33+
; CHECK: %3:gprc = LI 1
34+
%3:gprc = ORI killed %2:gprc, 1
35+
; CHECK: STW killed %3, %0, 100
36+
STW killed %3:gprc, %0:gprc, 100
37+
BLR8 implicit $lr8, implicit $rm
38+
...

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