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[X86][MC] Support encoding/decoding for APX variant MUL/IMUL/DIV/IDIV instructions (#76919)
Four variants: promoted legacy, ND (new data destination), NF (no flags update) and NF_ND (NF + ND). The syntax of NF instructions is aligned with GNU binutils. https://sourceware.org/pipermail/binutils/2023-September/129545.html
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‎llvm/lib/Target/X86/X86InstrArithmetic.td

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‎llvm/lib/Target/X86/X86InstrPredicates.td

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def TruePredicate : Predicate<"true">;
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// Intel x86 instructions have three separate encoding spaces: legacy, VEX, and
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// EVEX. Not all X86 instructions are extended for EGPR. The following is an
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// overview of which instructions are extended and how we implement them.
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//
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// * Legacy space
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// All instructions in legacy maps 0 and 1 that have explicit GPR or memory
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// operands can use the REX2 prefix to access the EGPR, except XSAVE*/XRSTOR.
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//
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// * EVEX space
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// All instructions in the EVEX space can access the EGPR in their
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// register/memory operands.
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//
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// For the above intructions, the only difference in encoding is reflected in
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// the REX2/EVEX prefix when EGPR is used, i.e. the opcode and opcode name are
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// unchanged. We don’t add new entries in TD, and instead we extend GPR with
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// R16-R31 and make them allocatable only when the feature EGPR is available.
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//
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// Besides, some instructions in legacy space with map 2/3 and VEX space are
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// promoted into EVEX space. Encoding space changes after the promotion, opcode
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// and opcode map may change too sometimes. For these instructions, we add new
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// entries in TD to avoid overcomplicating the assembler and disassembler.
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//
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// HasEGPR is for the new entries and NoEGPR is for the entries before
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// promotion, so that the promoted variant can be selected first to benefit RA.
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def HasEGPR : Predicate<"Subtarget->hasEGPR()">;
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def NoEGPR : Predicate<"!Subtarget->hasEGPR()">;
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// APX extends some instructions with a new form that has an extra register
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// operand called a new data destination (NDD). In such forms, NDD is the new
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// destination register receiving the result of the computation and all other
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// operands (including the original destination operand) become read-only source
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// operands.
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//
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// HasNDD is for the new NDD entries and NoNDD is for the legacy 2-address
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// entries, so that the NDD variant can be selected first to benefit RA.
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def HasNDD : Predicate<"Subtarget->hasNDD()">;
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def NoNDD : Predicate<"!Subtarget->hasNDD()">;
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def HasCMOV : Predicate<"Subtarget->canUseCMOV()">;

‎llvm/test/MC/Disassembler/X86/apx/div.txt

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# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT
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# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL
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# ATT: {evex} divb %bl
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# INTEL: {evex} div bl
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0x62,0xf4,0x7c,0x08,0xf6,0xf3
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# ATT: {nf} divb %bl
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# INTEL: {nf} div bl
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0x62,0xf4,0x7c,0x0c,0xf6,0xf3
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# ATT: {evex} divw %dx
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# INTEL: {evex} div dx
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0x62,0xf4,0x7d,0x08,0xf7,0xf2
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# ATT: {nf} divw %dx
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# INTEL: {nf} div dx
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0x62,0xf4,0x7d,0x0c,0xf7,0xf2
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# ATT: {evex} divl %ecx
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# INTEL: {evex} div ecx
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0x62,0xf4,0x7c,0x08,0xf7,0xf1
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# ATT: {nf} divl %ecx
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# INTEL: {nf} div ecx
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0x62,0xf4,0x7c,0x0c,0xf7,0xf1
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# ATT: {evex} divq %r9
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# INTEL: {evex} div r9
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0x62,0xd4,0xfc,0x08,0xf7,0xf1
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# ATT: {nf} divq %r9
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# INTEL: {nf} div r9
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0x62,0xd4,0xfc,0x0c,0xf7,0xf1
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# ATT: {evex} divb 291(%r8,%rax,4)
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# INTEL: {evex} div byte ptr [r8 + 4*rax + 291]
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0x62,0xd4,0x7c,0x08,0xf6,0xb4,0x80,0x23,0x01,0x00,0x00
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# ATT: {nf} divb 291(%r8,%rax,4)
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# INTEL: {nf} div byte ptr [r8 + 4*rax + 291]
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0x62,0xd4,0x7c,0x0c,0xf6,0xb4,0x80,0x23,0x01,0x00,0x00
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# ATT: {evex} divw 291(%r8,%rax,4)
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# INTEL: {evex} div word ptr [r8 + 4*rax + 291]
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0x62,0xd4,0x7d,0x08,0xf7,0xb4,0x80,0x23,0x01,0x00,0x00
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# ATT: {nf} divw 291(%r8,%rax,4)
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# INTEL: {nf} div word ptr [r8 + 4*rax + 291]
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0x62,0xd4,0x7d,0x0c,0xf7,0xb4,0x80,0x23,0x01,0x00,0x00
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# ATT: {evex} divl 291(%r8,%rax,4)
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# INTEL: {evex} div dword ptr [r8 + 4*rax + 291]
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0x62,0xd4,0x7c,0x08,0xf7,0xb4,0x80,0x23,0x01,0x00,0x00
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# ATT: {nf} divl 291(%r8,%rax,4)
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# INTEL: {nf} div dword ptr [r8 + 4*rax + 291]
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0x62,0xd4,0x7c,0x0c,0xf7,0xb4,0x80,0x23,0x01,0x00,0x00
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# ATT: {evex} divq 291(%r8,%rax,4)
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# INTEL: {evex} div qword ptr [r8 + 4*rax + 291]
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0x62,0xd4,0xfc,0x08,0xf7,0xb4,0x80,0x23,0x01,0x00,0x00
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# ATT: {nf} divq 291(%r8,%rax,4)
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# INTEL: {nf} div qword ptr [r8 + 4*rax + 291]
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0x62,0xd4,0xfc,0x0c,0xf7,0xb4,0x80,0x23,0x01,0x00,0x00

‎llvm/test/MC/Disassembler/X86/apx/idiv.txt

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# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT
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# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL
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# ATT: {evex} idivb %bl
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# INTEL: {evex} idiv bl
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0x62,0xf4,0x7c,0x08,0xf6,0xfb
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# ATT: {nf} idivb %bl
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# INTEL: {nf} idiv bl
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0x62,0xf4,0x7c,0x0c,0xf6,0xfb
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# ATT: {evex} idivw %dx
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# INTEL: {evex} idiv dx
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0x62,0xf4,0x7d,0x08,0xf7,0xfa
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# ATT: {nf} idivw %dx
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# INTEL: {nf} idiv dx
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0x62,0xf4,0x7d,0x0c,0xf7,0xfa
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# ATT: {evex} idivl %ecx
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# INTEL: {evex} idiv ecx
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0x62,0xf4,0x7c,0x08,0xf7,0xf9
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# ATT: {nf} idivl %ecx
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# INTEL: {nf} idiv ecx
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0x62,0xf4,0x7c,0x0c,0xf7,0xf9
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# ATT: {evex} idivq %r9
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# INTEL: {evex} idiv r9
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0x62,0xd4,0xfc,0x08,0xf7,0xf9
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# ATT: {nf} idivq %r9
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# INTEL: {nf} idiv r9
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0x62,0xd4,0xfc,0x0c,0xf7,0xf9
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# ATT: {evex} idivb 291(%r8,%rax,4)
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# INTEL: {evex} idiv byte ptr [r8 + 4*rax + 291]
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0x62,0xd4,0x7c,0x08,0xf6,0xbc,0x80,0x23,0x01,0x00,0x00
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# ATT: {nf} idivb 291(%r8,%rax,4)
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# INTEL: {nf} idiv byte ptr [r8 + 4*rax + 291]
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0x62,0xd4,0x7c,0x0c,0xf6,0xbc,0x80,0x23,0x01,0x00,0x00
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# ATT: {evex} idivw 291(%r8,%rax,4)
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# INTEL: {evex} idiv word ptr [r8 + 4*rax + 291]
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0x62,0xd4,0x7d,0x08,0xf7,0xbc,0x80,0x23,0x01,0x00,0x00
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# ATT: {nf} idivw 291(%r8,%rax,4)
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# INTEL: {nf} idiv word ptr [r8 + 4*rax + 291]
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0x62,0xd4,0x7d,0x0c,0xf7,0xbc,0x80,0x23,0x01,0x00,0x00
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# ATT: {evex} idivl 291(%r8,%rax,4)
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# INTEL: {evex} idiv dword ptr [r8 + 4*rax + 291]
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0x62,0xd4,0x7c,0x08,0xf7,0xbc,0x80,0x23,0x01,0x00,0x00
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# ATT: {nf} idivl 291(%r8,%rax,4)
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# INTEL: {nf} idiv dword ptr [r8 + 4*rax + 291]
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0x62,0xd4,0x7c,0x0c,0xf7,0xbc,0x80,0x23,0x01,0x00,0x00
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# ATT: {evex} idivq 291(%r8,%rax,4)
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# INTEL: {evex} idiv qword ptr [r8 + 4*rax + 291]
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0x62,0xd4,0xfc,0x08,0xf7,0xbc,0x80,0x23,0x01,0x00,0x00
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# ATT: {nf} idivq 291(%r8,%rax,4)
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# INTEL: {nf} idiv qword ptr [r8 + 4*rax + 291]
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0x62,0xd4,0xfc,0x0c,0xf7,0xbc,0x80,0x23,0x01,0x00,0x00

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