[RISCV][Scheduler] Add scheduler definitions for the Q extension

el-ev · el-ev · commit 4e01f6071209 · 2025-05-12T15:29:29.000+08:00
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
@@ -25,95 +25,119 @@ defvar QExtsRV64 = [QExt];
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtQ] in {
-  let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
-  def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd),
-              (ins GPRMem:$rs1, simm12:$imm12),
-              "flq", "$rd, ${imm12}(${rs1})">;
+  def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
+
   // Operands for stores are in the order srcreg, base, offset rather than
   // reflecting the order these fields are specified in the instruction
   // encoding.
-  let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
-  def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs),
-              (ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12),
-              "fsq", "$rs2, ${imm12}(${rs1})">;
+  def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
 } // Predicates = [HasStdExtQ]
 
 foreach Ext = QExts in {
-  defm FMADD_Q : FPFMA_rrr_frm_m<OPC_MADD, 0b11, "fmadd.q", Ext>;
-  defm FMSUB_Q : FPFMA_rrr_frm_m<OPC_MSUB, 0b11, "fmsub.q", Ext>;
-  defm FNMSUB_Q : FPFMA_rrr_frm_m<OPC_NMSUB, 0b11, "fnmsub.q", Ext>;
-  defm FNMADD_Q : FPFMA_rrr_frm_m<OPC_NMADD, 0b11, "fnmadd.q", Ext>;
+  let SchedRW = [WriteFMA128, ReadFMA128, ReadFMA128, ReadFMA128Addend] in {
+    defm FMADD_Q : FPFMA_rrr_frm_m<OPC_MADD, 0b11, "fmadd.q", Ext>;
+    defm FMSUB_Q : FPFMA_rrr_frm_m<OPC_MSUB, 0b11, "fmsub.q", Ext>;
+    defm FNMSUB_Q : FPFMA_rrr_frm_m<OPC_NMSUB, 0b11, "fnmsub.q", Ext>;
+    defm FNMADD_Q : FPFMA_rrr_frm_m<OPC_NMADD, 0b11, "fnmadd.q", Ext>;
+  }
 
-  defm FADD_Q : FPALU_rr_frm_m<0b0000011, "fadd.q", Ext>;
-  defm FSUB_Q : FPALU_rr_frm_m<0b0000111, "fsub.q", Ext>;
+  let SchedRW = [WriteFAdd128, ReadFAdd128, ReadFAdd128] in {
+    defm FADD_Q : FPALU_rr_frm_m<0b0000011, "fadd.q", Ext>;
+    defm FSUB_Q : FPALU_rr_frm_m<0b0000111, "fsub.q", Ext>;
+  }
 
+  let SchedRW = [WriteFMul128, ReadFMul128, ReadFMul128] in 
   defm FMUL_Q : FPALU_rr_frm_m<0b0001011, "fmul.q", Ext>;
 
+  let SchedRW = [WriteFDiv128, ReadFDiv128, ReadFDiv128] in 
   defm FDIV_Q : FPALU_rr_frm_m<0b0001111, "fdiv.q", Ext>;
 
   defm FSQRT_Q : FPUnaryOp_r_frm_m<0b0101111, 0b00000, Ext, Ext.PrimaryTy,
-                                   Ext.PrimaryTy, "fsqrt.q">;
+                                   Ext.PrimaryTy, "fsqrt.q">,
+                 Sched<[WriteFSqrt128, ReadFSqrt128]>;
 
-  let mayRaiseFPException = 0 in {
+  let SchedRW = [WriteFSGNJ128, ReadFSGNJ128, ReadFSGNJ128],
+      mayRaiseFPException = 0 in {
     defm FSGNJ_Q : FPALU_rr_m<0b0010011, 0b000, "fsgnj.q", Ext>;
     defm FSGNJN_Q : FPALU_rr_m<0b0010011, 0b001, "fsgnjn.q", Ext>;
     defm FSGNJX_Q : FPALU_rr_m<0b0010011, 0b010, "fsgnjx.q", Ext>;
   }
 
-  defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
-  defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+  let SchedRW = [WriteFMinMax128, ReadFMinMax128, ReadFMinMax128] in {
+    defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
+    defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+  }
 
   defm FCVT_S_Q : FPUnaryOp_r_frm_m<0b0100000, 0b00011, Ext, Ext.F32Ty,
-                                    Ext.PrimaryTy, "fcvt.s.q">;
+                                    Ext.PrimaryTy, "fcvt.s.q">,
+                  Sched<[WriteFCvtF128ToF32, ReadFCvtF128ToF32]>;
 
   defm FCVT_Q_S : FPUnaryOp_r_frmlegacy_m<0b0100011, 0b00000, Ext,
-                                          Ext.PrimaryTy, Ext.F32Ty, "fcvt.q.s">;
+                                          Ext.PrimaryTy, Ext.F32Ty, 
+                                          "fcvt.q.s">,
+                  Sched<[WriteFCvtF32ToF128, ReadFCvtF32ToF128]>;
 
   defm FCVT_D_Q : FPUnaryOp_r_frm_m<0b0100001, 0b00011, Ext, Ext.F64Ty,
-                                    Ext.PrimaryTy, "fcvt.d.q">;
+                                    Ext.PrimaryTy, "fcvt.d.q">,
+                  Sched<[WriteFCvtF128ToF64, ReadFCvtF128ToF64]>;
 
   defm FCVT_Q_D : FPUnaryOp_r_frmlegacy_m<0b0100011, 0b00001, Ext,
-                                          Ext.PrimaryTy, Ext.F64Ty, "fcvt.q.d">;
-
-  defm FEQ_Q : FPCmp_rr_m<0b1010011, 0b010, "feq.q", Ext, Commutable = 1>;
-  defm FLT_Q : FPCmp_rr_m<0b1010011, 0b001, "flt.q", Ext>;
-  defm FLE_Q : FPCmp_rr_m<0b1010011, 0b000, "fle.q", Ext>;
+                                          Ext.PrimaryTy, Ext.F64Ty, 
+                                          "fcvt.q.d">,
+                  Sched<[WriteFCvtF64ToF128, ReadFCvtF64ToF128]>;
+
+  let SchedRW = [WriteFCmp128, ReadFCmp128, ReadFCmp128] in {
+    defm FEQ_Q : FPCmp_rr_m<0b1010011, 0b010, "feq.q", Ext, Commutable = 1>;
+    defm FLT_Q : FPCmp_rr_m<0b1010011, 0b001, "flt.q", Ext>;
+    defm FLE_Q : FPCmp_rr_m<0b1010011, 0b000, "fle.q", Ext>;
+  }
 
   let mayRaiseFPException = 0 in 
   defm FCLASS_Q : FPUnaryOp_r_m<0b1110011, 0b00000, 0b001, Ext, GPR,
-                                Ext.PrimaryTy, "fclass.q">;
+                                Ext.PrimaryTy, "fclass.q">,
+                  Sched<[WriteFClass128, ReadFClass128]>;
 
   let IsSignExtendingOpW = 1 in 
   defm FCVT_W_Q  : FPUnaryOp_r_frm_m<0b1100011, 0b00000, Ext, GPR,
-                                     Ext.PrimaryTy, "fcvt.w.q">;
+                                     Ext.PrimaryTy, "fcvt.w.q">,
+                   Sched<[WriteFCvtF128ToI32, ReadFCvtF128ToI32]>;
 
   let IsSignExtendingOpW = 1 in 
   defm FCVT_WU_Q : FPUnaryOp_r_frm_m<0b1100011, 0b00001, Ext, GPR,
-                                     Ext.PrimaryTy, "fcvt.wu.q">;
+                                     Ext.PrimaryTy, "fcvt.wu.q">,
+                   Sched<[WriteFCvtF128ToI32, ReadFCvtF128ToI32]>;
 
   let mayRaiseFPException = 0 in 
   defm FCVT_Q_W  : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00000, Ext,
-                                     Ext.PrimaryTy, GPR, "fcvt.q.w">;
+                                     Ext.PrimaryTy, GPR, "fcvt.q.w">,
+                   Sched<[WriteFCvtI32ToF128, ReadFCvtI32ToF128]>;
 
   let mayRaiseFPException = 0 in 
   defm FCVT_Q_WU : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00001, Ext,
-                                     Ext.PrimaryTy, GPR, "fcvt.q.wu">;
+                                     Ext.PrimaryTy, GPR, "fcvt.q.wu">,
+                   Sched<[WriteFCvtI32ToF128, ReadFCvtI32ToF128]>;
 } // foreach Ext = QExts
 
 foreach Ext = QExtsRV64 in {
   defm FCVT_L_Q  : FPUnaryOp_r_frm_m<0b1100011, 0b00010, Ext, GPR, 
-                                     Ext.PrimaryTy, "fcvt.l.q", [IsRV64]>;
+                                     Ext.PrimaryTy, "fcvt.l.q", [IsRV64]>,
+                   Sched<[WriteFCvtF128ToI64, ReadFCvtF128ToI64]>;
 
   defm FCVT_LU_Q : FPUnaryOp_r_frm_m<0b1100011, 0b00011, Ext, GPR,
-                                     Ext.PrimaryTy, "fcvt.lu.q", [IsRV64]>;
+                                     Ext.PrimaryTy, "fcvt.lu.q", [IsRV64]>,
+                   Sched<[WriteFCvtF128ToI64, ReadFCvtF128ToI64]>;
 
   let mayRaiseFPException = 0 in 
-  defm FCVT_Q_L : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00010, Ext, Ext.PrimaryTy, 
-                                    GPR, "fcvt.q.l", [IsRV64]>;
+  defm FCVT_Q_L : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00010, Ext,
+                                          Ext.PrimaryTy, GPR, "fcvt.q.l",
+                                          [IsRV64]>,
+                  Sched<[WriteFCvtI64ToF128, ReadFCvtI64ToF128]>;
 
   let mayRaiseFPException = 0 in 
-  defm FCVT_Q_LU : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00011, Ext, Ext.PrimaryTy, 
-                                     GPR, "fcvt.q.lu", [IsRV64]>;
+  defm FCVT_Q_LU : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00011, Ext,
+                                           Ext.PrimaryTy, GPR, "fcvt.q.lu",
+                                           [IsRV64]>,
+                   Sched<[WriteFCvtI64ToF128, ReadFCvtI64ToF128]>;
 } // foreach Ext = QExtsRV64
 
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td b/llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
@@ -492,6 +492,7 @@ def : ReadAdvance<ReadFSqrt16, 0>;
 //===----------------------------------------------------------------------===//
 // Unsupported extensions
 //===----------------------------------------------------------------------===//
+defm : UnsupportedSchedQ;
 defm : UnsupportedSchedV;
 defm : UnsupportedSchedZvk;
 defm : UnsupportedSchedSFB;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td b/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
@@ -263,6 +263,7 @@ def : ReadAdvance<ReadIRem, 0>;
 def : ReadAdvance<ReadIRem32, 0>;
 
 // Unsupported extensions.
+defm : UnsupportedSchedQ;
 defm : UnsupportedSchedV;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbs;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
@@ -250,6 +250,7 @@ def : ReadAdvance<ReadFClass64, 0>;
 
 //===----------------------------------------------------------------------===//
 // Unsupported extensions
+defm : UnsupportedSchedQ;
 defm : UnsupportedSchedV;
 defm : UnsupportedSchedZabha;
 defm : UnsupportedSchedZba;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -1300,6 +1300,7 @@ foreach mx = SchedMxList in {
 
 //===----------------------------------------------------------------------===//
 // Unsupported extensions
+defm : UnsupportedSchedQ;
 defm : UnsupportedSchedZabha;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbkb;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
@@ -1231,6 +1231,7 @@ defm "" : LMULReadAdvance<"ReadVSM3MEV", 0>;
 
 //===----------------------------------------------------------------------===//
 // Unsupported extensions
+defm : UnsupportedSchedQ;
 defm : UnsupportedSchedZabha;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbkb;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
@@ -348,6 +348,7 @@ def : ReadAdvance<ReadSHXADD32, 0>;
 
 //===----------------------------------------------------------------------===//
 // Unsupported extensions
+defm : UnsupportedSchedQ;
 defm : UnsupportedSchedV;
 defm : UnsupportedSchedZabha;
 defm : UnsupportedSchedZbc;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
@@ -1487,6 +1487,7 @@ defm "" : LMULReadAdvance<"ReadVSM3MEV", 0>;
 
 //===----------------------------------------------------------------------===//
 // Unsupported extensions
+defm : UnsupportedSchedQ;
 defm : UnsupportedSchedZabha;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbkb;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
@@ -342,6 +342,7 @@ def : ReadAdvance<ReadSingleBitImm, 0>;
 
 //===----------------------------------------------------------------------===//
 // Unsupported extensions
+defm : UnsupportedSchedQ;
 defm : UnsupportedSchedV;
 defm : UnsupportedSchedXsfvcp;
 defm : UnsupportedSchedZabha;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td
@@ -199,6 +199,7 @@ multiclass SCR3_Unsupported :
 
 multiclass SCR4_SCR5_Unsupported :
   SCR_Unsupported,
+  UnsupportedSchedQ,
   UnsupportedSchedZfhmin;
 
 // Bypasses (none)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td
@@ -241,6 +241,7 @@ multiclass SCR7_Other {
 
 // Unsupported scheduling classes for SCR7.
 multiclass SCR7_Unsupported {
+  defm : UnsupportedSchedQ;
   defm : UnsupportedSchedSFB;
   defm : UnsupportedSchedV;
   defm : UnsupportedSchedXsfvcp;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
@@ -318,6 +318,7 @@ def : ReadAdvance<ReadSingleBitImm, 0>;
 
 //===----------------------------------------------------------------------===//
 // Unsupported extensions
+defm : UnsupportedSchedQ;
 defm : UnsupportedSchedV;
 defm : UnsupportedSchedXsfvcp;
 defm : UnsupportedSchedZabha;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td b/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
@@ -306,6 +306,7 @@ def : ReadAdvance<ReadXPERM, 0>;
 
 //===----------------------------------------------------------------------===//
 // Unsupported extensions
+defm : UnsupportedSchedQ;
 defm : UnsupportedSchedV;
 defm : UnsupportedSchedZfa;
 defm : UnsupportedSchedZfhmin;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedule.td b/llvm/lib/Target/RISCV/RISCVSchedule.td
