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AZero13AZero13
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[SelectionDAG] Switch to LiveRegUnits (#84197)
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7 files changed

+8
-26
lines changed

7 files changed

+8
-26
lines changed

‎llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@
2020
#include "llvm/ADT/SparseMultiSet.h"
2121
#include "llvm/ADT/SparseSet.h"
2222
#include "llvm/ADT/identity.h"
23-
#include "llvm/CodeGen/LivePhysRegs.h"
23+
#include "llvm/CodeGen/LiveRegUnits.h"
2424
#include "llvm/CodeGen/MachineBasicBlock.h"
2525
#include "llvm/CodeGen/ScheduleDAG.h"
2626
#include "llvm/CodeGen/TargetRegisterInfo.h"
@@ -263,7 +263,7 @@ namespace llvm {
263263
MachineInstr *FirstDbgValue = nullptr;
264264

265265
/// Set of live physical registers for updating kill flags.
266-
LivePhysRegs LiveRegs;
266+
LiveRegUnits LiveRegs;
267267

268268
public:
269269
explicit ScheduleDAGInstrs(MachineFunction &mf,

‎llvm/lib/CodeGen/ScheduleDAGInstrs.cpp

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1103,7 +1103,7 @@ void ScheduleDAGInstrs::reduceHugeMemNodeMaps(Value2SUsMap &stores,
11031103
dbgs() << "Loading SUnits:\n"; loads.dump());
11041104
}
11051105

1106-
static void toggleKills(const MachineRegisterInfo &MRI, LivePhysRegs &LiveRegs,
1106+
static void toggleKills(const MachineRegisterInfo &MRI, LiveRegUnits &LiveRegs,
11071107
MachineInstr &MI, bool addToLiveRegs) {
11081108
for (MachineOperand &MO : MI.operands()) {
11091109
if (!MO.isReg() || !MO.readsReg())
@@ -1113,8 +1113,10 @@ static void toggleKills(const MachineRegisterInfo &MRI, LivePhysRegs &LiveRegs,
11131113
continue;
11141114

11151115
// Things that are available after the instruction are killed by it.
1116-
bool IsKill = LiveRegs.available(MRI, Reg);
1117-
MO.setIsKill(IsKill);
1116+
bool IsKill = LiveRegs.available(Reg);
1117+
1118+
// Exception: Do not kill reserved registers
1119+
MO.setIsKill(IsKill && !MRI.isReserved(Reg));
11181120
if (addToLiveRegs)
11191121
LiveRegs.addReg(Reg);
11201122
}
@@ -1144,7 +1146,7 @@ void ScheduleDAGInstrs::fixupKills(MachineBasicBlock &MBB) {
11441146
continue;
11451147
LiveRegs.removeReg(Reg);
11461148
} else if (MO.isRegMask()) {
1147-
LiveRegs.removeRegsInMask(MO);
1149+
LiveRegs.removeRegsNotPreserved(MO.getRegMask());
11481150
}
11491151
}
11501152

‎llvm/test/CodeGen/AMDGPU/add.ll

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1263,7 +1263,6 @@ define amdgpu_kernel void @add64_in_branch(ptr addrspace(1) %out, ptr addrspace(
12631263
; GFX10-NEXT: ; %bb.1: ; %else
12641264
; GFX10-NEXT: s_add_u32 s4, s4, s6
12651265
; GFX10-NEXT: s_addc_u32 s5, s5, s7
1266-
; GFX10-NEXT: s_mov_b32 s6, 0
12671266
; GFX10-NEXT: s_cbranch_execnz .LBB9_3
12681267
; GFX10-NEXT: .LBB9_2: ; %if
12691268
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
@@ -1275,7 +1274,6 @@ define amdgpu_kernel void @add64_in_branch(ptr addrspace(1) %out, ptr addrspace(
12751274
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
12761275
; GFX10-NEXT: s_endpgm
12771276
; GFX10-NEXT: .LBB9_4:
1278-
; GFX10-NEXT: s_mov_b32 s6, -1
12791277
; GFX10-NEXT: ; implicit-def: $sgpr4_sgpr5
12801278
; GFX10-NEXT: s_branch .LBB9_2
12811279
;
@@ -1288,7 +1286,6 @@ define amdgpu_kernel void @add64_in_branch(ptr addrspace(1) %out, ptr addrspace(
12881286
; GFX11-NEXT: ; %bb.1: ; %else
12891287
; GFX11-NEXT: s_add_u32 s4, s4, s6
12901288
; GFX11-NEXT: s_addc_u32 s5, s5, s7
1291-
; GFX11-NEXT: s_mov_b32 s6, 0
12921289
; GFX11-NEXT: s_cbranch_execnz .LBB9_3
12931290
; GFX11-NEXT: .LBB9_2: ; %if
12941291
; GFX11-NEXT: s_load_b64 s[4:5], s[2:3], 0x0
@@ -1301,7 +1298,6 @@ define amdgpu_kernel void @add64_in_branch(ptr addrspace(1) %out, ptr addrspace(
13011298
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
13021299
; GFX11-NEXT: s_endpgm
13031300
; GFX11-NEXT: .LBB9_4:
1304-
; GFX11-NEXT: s_mov_b32 s6, -1
13051301
; GFX11-NEXT: ; implicit-def: $sgpr4_sgpr5
13061302
; GFX11-NEXT: s_branch .LBB9_2
13071303
;
@@ -1313,7 +1309,6 @@ define amdgpu_kernel void @add64_in_branch(ptr addrspace(1) %out, ptr addrspace(
13131309
; GFX12-NEXT: s_cbranch_scc0 .LBB9_4
13141310
; GFX12-NEXT: ; %bb.1: ; %else
13151311
; GFX12-NEXT: s_add_nc_u64 s[4:5], s[4:5], s[6:7]
1316-
; GFX12-NEXT: s_mov_b32 s6, 0
13171312
; GFX12-NEXT: s_cbranch_execnz .LBB9_3
13181313
; GFX12-NEXT: .LBB9_2: ; %if
13191314
; GFX12-NEXT: s_load_b64 s[4:5], s[2:3], 0x0
@@ -1326,7 +1321,6 @@ define amdgpu_kernel void @add64_in_branch(ptr addrspace(1) %out, ptr addrspace(
13261321
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
13271322
; GFX12-NEXT: s_endpgm
13281323
; GFX12-NEXT: .LBB9_4:
1329-
; GFX12-NEXT: s_mov_b32 s6, -1
13301324
; GFX12-NEXT: ; implicit-def: $sgpr4_sgpr5
13311325
; GFX12-NEXT: s_branch .LBB9_2
13321326
entry:

‎llvm/test/CodeGen/AMDGPU/ctpop16.ll

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1499,7 +1499,6 @@ define amdgpu_kernel void @ctpop_i16_in_br(ptr addrspace(1) %out, ptr addrspace(
14991499
; SI-NEXT: s_mov_b32 s8, s2
15001500
; SI-NEXT: s_mov_b32 s9, s3
15011501
; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0 offset:2
1502-
; SI-NEXT: s_mov_b64 s[2:3], 0
15031502
; SI-NEXT: s_cbranch_execnz .LBB14_3
15041503
; SI-NEXT: .LBB14_2: ; %if
15051504
; SI-NEXT: s_and_b32 s2, s4, 0xffff
@@ -1513,7 +1512,6 @@ define amdgpu_kernel void @ctpop_i16_in_br(ptr addrspace(1) %out, ptr addrspace(
15131512
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
15141513
; SI-NEXT: s_endpgm
15151514
; SI-NEXT: .LBB14_4:
1516-
; SI-NEXT: s_mov_b64 s[2:3], -1
15171515
; SI-NEXT: v_mov_b32_e32 v0, 0
15181516
; SI-NEXT: s_branch .LBB14_2
15191517
;
@@ -1531,7 +1529,6 @@ define amdgpu_kernel void @ctpop_i16_in_br(ptr addrspace(1) %out, ptr addrspace(
15311529
; VI-NEXT: s_mov_b32 s8, s2
15321530
; VI-NEXT: s_mov_b32 s9, s3
15331531
; VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0 offset:2
1534-
; VI-NEXT: s_mov_b64 s[2:3], 0
15351532
; VI-NEXT: s_cbranch_execnz .LBB14_3
15361533
; VI-NEXT: .LBB14_2: ; %if
15371534
; VI-NEXT: s_and_b32 s2, s4, 0xffff
@@ -1545,7 +1542,6 @@ define amdgpu_kernel void @ctpop_i16_in_br(ptr addrspace(1) %out, ptr addrspace(
15451542
; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
15461543
; VI-NEXT: s_endpgm
15471544
; VI-NEXT: .LBB14_4:
1548-
; VI-NEXT: s_mov_b64 s[2:3], -1
15491545
; VI-NEXT: ; implicit-def: $vgpr0
15501546
; VI-NEXT: s_branch .LBB14_2
15511547
;

‎llvm/test/CodeGen/AMDGPU/ctpop64.ll

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -358,7 +358,6 @@ define amdgpu_kernel void @ctpop_i64_in_br(ptr addrspace(1) %out, ptr addrspace(
358358
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
359359
; SI-NEXT: s_endpgm
360360
; SI-NEXT: .LBB7_4:
361-
; SI-NEXT: s_mov_b64 s[6:7], -1
362361
; SI-NEXT: ; implicit-def: $sgpr0_sgpr1
363362
; SI-NEXT: s_branch .LBB7_2
364363
;
@@ -372,7 +371,6 @@ define amdgpu_kernel void @ctpop_i64_in_br(ptr addrspace(1) %out, ptr addrspace(
372371
; VI-NEXT: s_cbranch_scc0 .LBB7_4
373372
; VI-NEXT: ; %bb.1: ; %else
374373
; VI-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x8
375-
; VI-NEXT: s_mov_b64 s[6:7], 0
376374
; VI-NEXT: s_cbranch_execnz .LBB7_3
377375
; VI-NEXT: .LBB7_2: ; %if
378376
; VI-NEXT: s_waitcnt lgkmcnt(0)
@@ -387,7 +385,6 @@ define amdgpu_kernel void @ctpop_i64_in_br(ptr addrspace(1) %out, ptr addrspace(
387385
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
388386
; VI-NEXT: s_endpgm
389387
; VI-NEXT: .LBB7_4:
390-
; VI-NEXT: s_mov_b64 s[6:7], -1
391388
; VI-NEXT: ; implicit-def: $sgpr0_sgpr1
392389
; VI-NEXT: s_branch .LBB7_2
393390
entry:

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -100,7 +100,6 @@ define amdgpu_kernel void @set_inactive_scc(ptr addrspace(1) %out, i32 %in, <4 x
100100
; GCN-NEXT: s_mov_b32 s3, 0xf000
101101
; GCN-NEXT: s_mov_b32 s2, -1
102102
; GCN-NEXT: buffer_store_dword v1, off, s[0:3], 0
103-
; GCN-NEXT: s_mov_b64 s[2:3], 0
104103
; GCN-NEXT: s_cbranch_execnz .LBB4_2
105104
; GCN-NEXT: .LBB4_4: ; %.zero
106105
; GCN-NEXT: s_mov_b32 s3, 0xf000

‎llvm/test/CodeGen/AMDGPU/mul.ll

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2517,7 +2517,6 @@ define amdgpu_kernel void @mul64_in_branch(ptr addrspace(1) %out, ptr addrspace(
25172517
; GFX10-NEXT: s_add_i32 s7, s8, s7
25182518
; GFX10-NEXT: s_mul_i32 s4, s4, s6
25192519
; GFX10-NEXT: s_add_i32 s5, s7, s5
2520-
; GFX10-NEXT: s_mov_b32 s6, 0
25212520
; GFX10-NEXT: s_cbranch_execnz .LBB16_4
25222521
; GFX10-NEXT: .LBB16_2: ; %if
25232522
; GFX10-NEXT: s_mov_b32 s7, 0x31016000
@@ -2527,7 +2526,6 @@ define amdgpu_kernel void @mul64_in_branch(ptr addrspace(1) %out, ptr addrspace(
25272526
; GFX10-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0
25282527
; GFX10-NEXT: s_branch .LBB16_5
25292528
; GFX10-NEXT: .LBB16_3:
2530-
; GFX10-NEXT: s_mov_b32 s6, -1
25312529
; GFX10-NEXT: ; implicit-def: $sgpr4_sgpr5
25322530
; GFX10-NEXT: s_branch .LBB16_2
25332531
; GFX10-NEXT: .LBB16_4:
@@ -2553,7 +2551,6 @@ define amdgpu_kernel void @mul64_in_branch(ptr addrspace(1) %out, ptr addrspace(
25532551
; GFX11-NEXT: s_add_i32 s7, s8, s7
25542552
; GFX11-NEXT: s_mul_i32 s4, s4, s6
25552553
; GFX11-NEXT: s_add_i32 s5, s7, s5
2556-
; GFX11-NEXT: s_mov_b32 s6, 0
25572554
; GFX11-NEXT: s_cbranch_execnz .LBB16_4
25582555
; GFX11-NEXT: .LBB16_2: ; %if
25592556
; GFX11-NEXT: s_mov_b32 s7, 0x31016000
@@ -2563,7 +2560,6 @@ define amdgpu_kernel void @mul64_in_branch(ptr addrspace(1) %out, ptr addrspace(
25632560
; GFX11-NEXT: buffer_load_b64 v[0:1], off, s[4:7], 0
25642561
; GFX11-NEXT: s_branch .LBB16_5
25652562
; GFX11-NEXT: .LBB16_3:
2566-
; GFX11-NEXT: s_mov_b32 s6, -1
25672563
; GFX11-NEXT: ; implicit-def: $sgpr4_sgpr5
25682564
; GFX11-NEXT: s_branch .LBB16_2
25692565
; GFX11-NEXT: .LBB16_4:
@@ -2585,7 +2581,6 @@ define amdgpu_kernel void @mul64_in_branch(ptr addrspace(1) %out, ptr addrspace(
25852581
; GFX12-NEXT: s_cbranch_scc0 .LBB16_3
25862582
; GFX12-NEXT: ; %bb.1: ; %else
25872583
; GFX12-NEXT: s_mul_u64 s[4:5], s[4:5], s[6:7]
2588-
; GFX12-NEXT: s_mov_b32 s6, 0
25892584
; GFX12-NEXT: s_cbranch_execnz .LBB16_4
25902585
; GFX12-NEXT: .LBB16_2: ; %if
25912586
; GFX12-NEXT: s_mov_b32 s7, 0x31016000
@@ -2595,7 +2590,6 @@ define amdgpu_kernel void @mul64_in_branch(ptr addrspace(1) %out, ptr addrspace(
25952590
; GFX12-NEXT: buffer_load_b64 v[0:1], off, s[4:7], null
25962591
; GFX12-NEXT: s_branch .LBB16_5
25972592
; GFX12-NEXT: .LBB16_3:
2598-
; GFX12-NEXT: s_mov_b32 s6, -1
25992593
; GFX12-NEXT: ; implicit-def: $sgpr4_sgpr5
26002594
; GFX12-NEXT: s_branch .LBB16_2
26012595
; GFX12-NEXT: .LBB16_4:

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