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davemgreendavemgreen
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[AArch64] Add GlobalISel coverage for BIT/BIF/BSL. NFC
Some of the 1x vector types are expanded to scalar, but the others that do not require constants looks OK.
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-719
lines changed

3 files changed

+1897
-719
lines changed

‎llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll

Lines changed: 64 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,27 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
2+
; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3+
; RUN: llc -mtriple=aarch64-unknown-linux-gnu -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
34

45
; BIF Bitwise Insert if False
56
;
67
; 8-bit vectors tests
78

89
define <1 x i8> @test_bitf_v1i8(<1 x i8> %A, <1 x i8> %B, <1 x i8> %C) {
9-
; CHECK-LABEL: test_bitf_v1i8:
10-
; CHECK: // %bb.0:
11-
; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b
12-
; CHECK-NEXT: ret
10+
; CHECK-SD-LABEL: test_bitf_v1i8:
11+
; CHECK-SD: // %bb.0:
12+
; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b
13+
; CHECK-SD-NEXT: ret
14+
;
15+
; CHECK-GI-LABEL: test_bitf_v1i8:
16+
; CHECK-GI: // %bb.0:
17+
; CHECK-GI-NEXT: fmov x8, d0
18+
; CHECK-GI-NEXT: fmov x9, d1
19+
; CHECK-GI-NEXT: fmov x10, d2
20+
; CHECK-GI-NEXT: bic w9, w9, w10
21+
; CHECK-GI-NEXT: and w8, w10, w8
22+
; CHECK-GI-NEXT: orr w8, w9, w8
23+
; CHECK-GI-NEXT: fmov s0, w8
24+
; CHECK-GI-NEXT: ret
1325
%neg = xor <1 x i8> %C, <i8 -1>
1426
%and = and <1 x i8> %neg, %B
1527
%and1 = and <1 x i8> %C, %A
@@ -20,10 +32,21 @@ define <1 x i8> @test_bitf_v1i8(<1 x i8> %A, <1 x i8> %B, <1 x i8> %C) {
2032
; 16-bit vectors tests
2133

2234
define <1 x i16> @test_bitf_v1i16(<1 x i16> %A, <1 x i16> %B, <1 x i16> %C) {
23-
; CHECK-LABEL: test_bitf_v1i16:
24-
; CHECK: // %bb.0:
25-
; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b
26-
; CHECK-NEXT: ret
35+
; CHECK-SD-LABEL: test_bitf_v1i16:
36+
; CHECK-SD: // %bb.0:
37+
; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b
38+
; CHECK-SD-NEXT: ret
39+
;
40+
; CHECK-GI-LABEL: test_bitf_v1i16:
41+
; CHECK-GI: // %bb.0:
42+
; CHECK-GI-NEXT: fmov x8, d0
43+
; CHECK-GI-NEXT: fmov x9, d1
44+
; CHECK-GI-NEXT: fmov x10, d2
45+
; CHECK-GI-NEXT: bic w9, w9, w10
46+
; CHECK-GI-NEXT: and w8, w10, w8
47+
; CHECK-GI-NEXT: orr w8, w9, w8
48+
; CHECK-GI-NEXT: fmov s0, w8
49+
; CHECK-GI-NEXT: ret
2750
%neg = xor <1 x i16> %C, <i16 -1>
2851
%and = and <1 x i16> %neg, %B
2952
%and1 = and <1 x i16> %C, %A
@@ -34,10 +57,23 @@ define <1 x i16> @test_bitf_v1i16(<1 x i16> %A, <1 x i16> %B, <1 x i16> %C) {
3457
; 32-bit vectors tests
3558

3659
define <1 x i32> @test_bitf_v1i32(<1 x i32> %A, <1 x i32> %B, <1 x i32> %C) {
37-
; CHECK-LABEL: test_bitf_v1i32:
38-
; CHECK: // %bb.0:
39-
; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b
40-
; CHECK-NEXT: ret
60+
; CHECK-SD-LABEL: test_bitf_v1i32:
61+
; CHECK-SD: // %bb.0:
62+
; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b
63+
; CHECK-SD-NEXT: ret
64+
;
65+
; CHECK-GI-LABEL: test_bitf_v1i32:
66+
; CHECK-GI: // %bb.0:
67+
; CHECK-GI-NEXT: fmov x8, d0
68+
; CHECK-GI-NEXT: fmov x9, d1
69+
; CHECK-GI-NEXT: fmov x10, d2
70+
; CHECK-GI-NEXT: bic w9, w9, w10
71+
; CHECK-GI-NEXT: and w8, w10, w8
72+
; CHECK-GI-NEXT: orr w8, w9, w8
73+
; CHECK-GI-NEXT: fmov s0, w8
74+
; CHECK-GI-NEXT: mov v0.s[1], w8
75+
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
76+
; CHECK-GI-NEXT: ret
4177
%neg = xor <1 x i32> %C, <i32 -1>
4278
%and = and <1 x i32> %neg, %B
4379
%and1 = and <1 x i32> %C, %A
@@ -48,10 +84,21 @@ define <1 x i32> @test_bitf_v1i32(<1 x i32> %A, <1 x i32> %B, <1 x i32> %C) {
4884
; 64-bit vectors tests
4985

5086
define <1 x i64> @test_bitf_v1i64(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C) {
51-
; CHECK-LABEL: test_bitf_v1i64:
52-
; CHECK: // %bb.0:
53-
; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b
54-
; CHECK-NEXT: ret
87+
; CHECK-SD-LABEL: test_bitf_v1i64:
88+
; CHECK-SD: // %bb.0:
89+
; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b
90+
; CHECK-SD-NEXT: ret
91+
;
92+
; CHECK-GI-LABEL: test_bitf_v1i64:
93+
; CHECK-GI: // %bb.0:
94+
; CHECK-GI-NEXT: fmov x8, d2
95+
; CHECK-GI-NEXT: fmov x9, d1
96+
; CHECK-GI-NEXT: fmov x10, d0
97+
; CHECK-GI-NEXT: bic x9, x9, x8
98+
; CHECK-GI-NEXT: and x8, x8, x10
99+
; CHECK-GI-NEXT: orr x8, x9, x8
100+
; CHECK-GI-NEXT: fmov d0, x8
101+
; CHECK-GI-NEXT: ret
55102
%neg = xor <1 x i64> %C, <i64 -1>
56103
%and = and <1 x i64> %neg, %B
57104
%and1 = and <1 x i64> %C, %A

‎llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll

Lines changed: 66 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,29 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
2+
; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3+
; RUN: llc -mtriple=aarch64-unknown-linux-gnu -global-isel -global-isel-abort=2 < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
4+
5+
; CHECK-GI: warning: Instruction selection used fallback path for test_bit_sink_operand
36

47
; BIT Bitwise Insert if True
58
;
69
; 8-bit vectors tests
710

811
define <1 x i8> @test_bit_v1i8(<1 x i8> %A, <1 x i8> %B, <1 x i8> %C) {
9-
; CHECK-LABEL: test_bit_v1i8:
10-
; CHECK: // %bb.0:
11-
; CHECK-NEXT: bit v0.8b, v1.8b, v2.8b
12-
; CHECK-NEXT: ret
12+
; CHECK-SD-LABEL: test_bit_v1i8:
13+
; CHECK-SD: // %bb.0:
14+
; CHECK-SD-NEXT: bit v0.8b, v1.8b, v2.8b
15+
; CHECK-SD-NEXT: ret
16+
;
17+
; CHECK-GI-LABEL: test_bit_v1i8:
18+
; CHECK-GI: // %bb.0:
19+
; CHECK-GI-NEXT: fmov x8, d0
20+
; CHECK-GI-NEXT: fmov x9, d1
21+
; CHECK-GI-NEXT: fmov x10, d2
22+
; CHECK-GI-NEXT: and w9, w10, w9
23+
; CHECK-GI-NEXT: bic w8, w8, w10
24+
; CHECK-GI-NEXT: orr w8, w9, w8
25+
; CHECK-GI-NEXT: fmov s0, w8
26+
; CHECK-GI-NEXT: ret
1327
%and = and <1 x i8> %C, %B
1428
%neg = xor <1 x i8> %C, <i8 -1>
1529
%and1 = and <1 x i8> %neg, %A
@@ -20,10 +34,21 @@ define <1 x i8> @test_bit_v1i8(<1 x i8> %A, <1 x i8> %B, <1 x i8> %C) {
2034
; 16-bit vectors tests
2135

2236
define <1 x i16> @test_bit_v1i16(<1 x i16> %A, <1 x i16> %B, <1 x i16> %C) {
23-
; CHECK-LABEL: test_bit_v1i16:
24-
; CHECK: // %bb.0:
25-
; CHECK-NEXT: bit v0.8b, v1.8b, v2.8b
26-
; CHECK-NEXT: ret
37+
; CHECK-SD-LABEL: test_bit_v1i16:
38+
; CHECK-SD: // %bb.0:
39+
; CHECK-SD-NEXT: bit v0.8b, v1.8b, v2.8b
40+
; CHECK-SD-NEXT: ret
41+
;
42+
; CHECK-GI-LABEL: test_bit_v1i16:
43+
; CHECK-GI: // %bb.0:
44+
; CHECK-GI-NEXT: fmov x8, d0
45+
; CHECK-GI-NEXT: fmov x9, d1
46+
; CHECK-GI-NEXT: fmov x10, d2
47+
; CHECK-GI-NEXT: and w9, w10, w9
48+
; CHECK-GI-NEXT: bic w8, w8, w10
49+
; CHECK-GI-NEXT: orr w8, w9, w8
50+
; CHECK-GI-NEXT: fmov s0, w8
51+
; CHECK-GI-NEXT: ret
2752
%and = and <1 x i16> %C, %B
2853
%neg = xor <1 x i16> %C, <i16 -1>
2954
%and1 = and <1 x i16> %neg, %A
@@ -34,10 +59,23 @@ define <1 x i16> @test_bit_v1i16(<1 x i16> %A, <1 x i16> %B, <1 x i16> %C) {
3459
; 32-bit vectors tests
3560

3661
define <1 x i32> @test_bit_v1i32(<1 x i32> %A, <1 x i32> %B, <1 x i32> %C) {
37-
; CHECK-LABEL: test_bit_v1i32:
38-
; CHECK: // %bb.0:
39-
; CHECK-NEXT: bit v0.8b, v1.8b, v2.8b
40-
; CHECK-NEXT: ret
62+
; CHECK-SD-LABEL: test_bit_v1i32:
63+
; CHECK-SD: // %bb.0:
64+
; CHECK-SD-NEXT: bit v0.8b, v1.8b, v2.8b
65+
; CHECK-SD-NEXT: ret
66+
;
67+
; CHECK-GI-LABEL: test_bit_v1i32:
68+
; CHECK-GI: // %bb.0:
69+
; CHECK-GI-NEXT: fmov x8, d0
70+
; CHECK-GI-NEXT: fmov x9, d1
71+
; CHECK-GI-NEXT: fmov x10, d2
72+
; CHECK-GI-NEXT: and w9, w10, w9
73+
; CHECK-GI-NEXT: bic w8, w8, w10
74+
; CHECK-GI-NEXT: orr w8, w9, w8
75+
; CHECK-GI-NEXT: fmov s0, w8
76+
; CHECK-GI-NEXT: mov v0.s[1], w8
77+
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
78+
; CHECK-GI-NEXT: ret
4179
%and = and <1 x i32> %C, %B
4280
%neg = xor <1 x i32> %C, <i32 -1>
4381
%and1 = and <1 x i32> %neg, %A
@@ -48,10 +86,21 @@ define <1 x i32> @test_bit_v1i32(<1 x i32> %A, <1 x i32> %B, <1 x i32> %C) {
4886
; 64-bit vectors tests
4987

5088
define <1 x i64> @test_bit_v1i64(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C) {
51-
; CHECK-LABEL: test_bit_v1i64:
52-
; CHECK: // %bb.0:
53-
; CHECK-NEXT: bit v0.8b, v1.8b, v2.8b
54-
; CHECK-NEXT: ret
89+
; CHECK-SD-LABEL: test_bit_v1i64:
90+
; CHECK-SD: // %bb.0:
91+
; CHECK-SD-NEXT: bit v0.8b, v1.8b, v2.8b
92+
; CHECK-SD-NEXT: ret
93+
;
94+
; CHECK-GI-LABEL: test_bit_v1i64:
95+
; CHECK-GI: // %bb.0:
96+
; CHECK-GI-NEXT: fmov x8, d2
97+
; CHECK-GI-NEXT: fmov x9, d1
98+
; CHECK-GI-NEXT: fmov x10, d0
99+
; CHECK-GI-NEXT: and x9, x8, x9
100+
; CHECK-GI-NEXT: bic x8, x10, x8
101+
; CHECK-GI-NEXT: orr x8, x9, x8
102+
; CHECK-GI-NEXT: fmov d0, x8
103+
; CHECK-GI-NEXT: ret
55104
%and = and <1 x i64> %C, %B
56105
%neg = xor <1 x i64> %C, <i64 -1>
57106
%and1 = and <1 x i64> %neg, %A

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