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diggerlindiggerlin
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introduce a ISD::POISON SDNode
1 parent 79e788d commit 4e80a92

13 files changed

+83
-20
lines changed

‎llvm/include/llvm/CodeGen/ISDOpcodes.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -217,6 +217,9 @@ enum NodeType {
217217
/// UNDEF - An undefined node.
218218
UNDEF,
219219

220+
/// POISON - A poison node.
221+
POISON,
222+
220223
/// FREEZE - FREEZE(VAL) returns an arbitrary value if VAL is UNDEF (or
221224
/// is evaluated to UNDEF), or returns VAL otherwise. Note that each
222225
/// read of UNDEF can yield different value, but FREEZE(UNDEF) cannot.

‎llvm/include/llvm/CodeGen/SelectionDAG.h

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -871,7 +871,7 @@ class SelectionDAG {
871871
/// for integers, a type wider than) VT's element type.
872872
SDValue getSplatBuildVector(EVT VT, const SDLoc &DL, SDValue Op) {
873873
// VerifySDNode (via InsertNode) checks BUILD_VECTOR later.
874-
if (Op.getOpcode() == ISD::UNDEF) {
874+
if (Op.isUndef()) {
875875
assert((VT.getVectorElementType() == Op.getValueType() ||
876876
(VT.isInteger() &&
877877
VT.getVectorElementType().bitsLE(Op.getValueType()))) &&
@@ -887,7 +887,7 @@ class SelectionDAG {
887887
// Return a splat ISD::SPLAT_VECTOR node, consisting of Op splatted to all
888888
// elements.
889889
SDValue getSplatVector(EVT VT, const SDLoc &DL, SDValue Op) {
890-
if (Op.getOpcode() == ISD::UNDEF) {
890+
if (Op.isUndef()) {
891891
assert((VT.getVectorElementType() == Op.getValueType() ||
892892
(VT.isInteger() &&
893893
VT.getVectorElementType().bitsLE(Op.getValueType()))) &&
@@ -1128,6 +1128,9 @@ class SelectionDAG {
11281128
return getNode(ISD::UNDEF, SDLoc(), VT);
11291129
}
11301130

1131+
/// Return an Poison node. POISON does not have a useful SDLoc.
1132+
SDValue getPoison(EVT VT) { return getNode(ISD::POISON, SDLoc(), VT); }
1133+
11311134
/// Return a node that represents the runtime scaling 'MulImm * RuntimeVL'.
11321135
SDValue getVScale(const SDLoc &DL, EVT VT, APInt MulImm,
11331136
bool ConstantFold = true);

‎llvm/include/llvm/CodeGen/SelectionDAGNodes.h

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -690,8 +690,17 @@ END_TWO_BYTE_PACK()
690690
/// \<target\>ISD namespace).
691691
bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
692692

693-
/// Return true if the type of the node type undefined.
694-
bool isUndef() const { return NodeType == ISD::UNDEF; }
693+
/// Returns true if the node type is UNDEF or, when UndefOnly is false,
694+
/// POISON.
695+
/// - When UndefOnly is true, returns true only for UNDEF.
696+
/// - When UndefOnly is false, returns true for both UNDEF and POISON.
697+
/// @param UndefOnly Determines whether to check only for UNDEF.
698+
bool isUndef(bool UndefOnly = false) const {
699+
return NodeType == ISD::UNDEF || (!UndefOnly && NodeType == ISD::POISON);
700+
}
701+
702+
/// Return true if the type of the node type poison.
703+
bool isPoison() const { return NodeType == ISD::POISON; }
695704

696705
/// Test if this node is a memory intrinsic (with valid pointer information).
697706
bool isMemIntrinsic() const { return SDNodeBits.IsMemIntrinsic; }

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -16156,7 +16156,7 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) {
1615616156
// also recursively replace t184 by t150.
1615716157
SDValue MaybePoisonOperand = N->getOperand(0).getOperand(OpNo);
1615816158
// Don't replace every single UNDEF everywhere with frozen UNDEF, though.
16159-
if (MaybePoisonOperand.getOpcode() == ISD::UNDEF)
16159+
if (MaybePoisonOperand.isUndef())
1616016160
continue;
1616116161
// First, freeze each offending operand.
1616216162
SDValue FrozenMaybePoisonOperand = DAG.getFreeze(MaybePoisonOperand);
@@ -16182,9 +16182,10 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) {
1618216182
// Finally, recreate the node, it's operands were updated to use
1618316183
// frozen operands, so we just need to use it's "original" operands.
1618416184
SmallVector<SDValue> Ops(N0->ops());
16185-
// Special-handle ISD::UNDEF, each single one of them can be it's own thing.
16185+
// Special-handle ISD::UNDEF, ISD::POISON, each single one of them can be it's
16186+
// own thing.
1618616187
for (SDValue &Op : Ops) {
16187-
if (Op.getOpcode() == ISD::UNDEF)
16188+
if (Op.isUndef())
1618816189
Op = DAG.getFreeze(Op);
1618916190
}
1619016191

@@ -24320,7 +24321,7 @@ static SDValue combineConcatVectorOfScalars(SDNode *N, SelectionDAG &DAG) {
2432024321
if (ISD::BITCAST == Op.getOpcode() &&
2432124322
!Op.getOperand(0).getValueType().isVector())
2432224323
Ops.push_back(Op.getOperand(0));
24323-
else if (ISD::UNDEF == Op.getOpcode())
24324+
else if (Op.isUndef())
2432424325
Ops.push_back(DAG.getNode(ISD::UNDEF, DL, SVT));
2432524326
else
2432624327
return SDValue();
@@ -24715,7 +24716,7 @@ SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
2471524716
// fold (concat_vectors (BUILD_VECTOR A, B, ...), (BUILD_VECTOR C, D, ...))
2471624717
// -> (BUILD_VECTOR A, B, ..., C, D, ...)
2471724718
auto IsBuildVectorOrUndef = [](const SDValue &Op) {
24718-
return ISD::UNDEF == Op.getOpcode() || ISD::BUILD_VECTOR == Op.getOpcode();
24719+
return Op.isUndef() || ISD::BUILD_VECTOR == Op.getOpcode();
2471924720
};
2472024721
if (llvm::all_of(N->ops(), IsBuildVectorOrUndef)) {
2472124722
SmallVector<SDValue, 8> Opnds;
@@ -24739,7 +24740,7 @@ SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
2473924740
EVT OpVT = Op.getValueType();
2474024741
unsigned NumElts = OpVT.getVectorNumElements();
2474124742

24742-
if (ISD::UNDEF == Op.getOpcode())
24743+
if (Op.isUndef())
2474324744
Opnds.append(NumElts, DAG.getUNDEF(MinVT));
2474424745

2474524746
if (ISD::BUILD_VECTOR == Op.getOpcode()) {

‎llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -977,6 +977,18 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
977977
TargetLowering::LegalizeAction Action = TargetLowering::Legal;
978978
bool SimpleFinishLegalizing = true;
979979
switch (Node->getOpcode()) {
980+
// FixMe: If the node represents a poison value, replace it with an undef
981+
// value.
982+
// A poison value results from an erroneous operation but does not cause
983+
// immediate undefined behavior, allowing speculative execution.
984+
// Since most operations propagate poison, it is valid to replace poison
985+
// with an undef value, which can take any legal value of the same type.
986+
// This ensures that downstream computations do not rely on poison semantics.
987+
case ISD::POISON: {
988+
SDValue UndefNode = DAG.getUNDEF(Node->getValueType(0));
989+
ReplaceNode(Node, UndefNode.getNode());
990+
break;
991+
}
980992
case ISD::INTRINSIC_W_CHAIN:
981993
case ISD::INTRINSIC_WO_CHAIN:
982994
case ISD::INTRINSIC_VOID:
@@ -3136,6 +3148,7 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
31363148
for (unsigned i = 0; i < Node->getNumValues(); i++)
31373149
Results.push_back(Node->getOperand(i));
31383150
break;
3151+
case ISD::POISON:
31393152
case ISD::UNDEF: {
31403153
EVT VT = Node->getValueType(0);
31413154
if (VT.isInteger())

‎llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -164,6 +164,7 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
164164
case ISD::STRICT_UINT_TO_FP:
165165
case ISD::SINT_TO_FP:
166166
case ISD::UINT_TO_FP: R = SoftenFloatRes_XINT_TO_FP(N); break;
167+
case ISD::POISON:
167168
case ISD::UNDEF: R = SoftenFloatRes_UNDEF(N); break;
168169
case ISD::VAARG: R = SoftenFloatRes_VAARG(N); break;
169170
case ISD::VECREDUCE_FADD:
@@ -1474,6 +1475,7 @@ void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) {
14741475
report_fatal_error("Do not know how to expand the result of this "
14751476
"operator!");
14761477
// clang-format off
1478+
case ISD::POISON:
14771479
case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
14781480
case ISD::SELECT: SplitRes_Select(N, Lo, Hi); break;
14791481
case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
@@ -2783,6 +2785,7 @@ void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) {
27832785

27842786
case ISD::SINT_TO_FP:
27852787
case ISD::UINT_TO_FP: R = PromoteFloatRes_XINT_TO_FP(N); break;
2788+
case ISD::POISON:
27862789
case ISD::UNDEF: R = PromoteFloatRes_UNDEF(N); break;
27872790
case ISD::ATOMIC_SWAP: R = BitcastToInt_ATOMIC_SWAP(N); break;
27882791
case ISD::VECREDUCE_FADD:
@@ -3242,6 +3245,7 @@ void DAGTypeLegalizer::SoftPromoteHalfResult(SDNode *N, unsigned ResNo) {
32423245
case ISD::STRICT_UINT_TO_FP:
32433246
case ISD::SINT_TO_FP:
32443247
case ISD::UINT_TO_FP: R = SoftPromoteHalfRes_XINT_TO_FP(N); break;
3248+
case ISD::POISON:
32453249
case ISD::UNDEF: R = SoftPromoteHalfRes_UNDEF(N); break;
32463250
case ISD::ATOMIC_SWAP: R = BitcastToInt_ATOMIC_SWAP(N); break;
32473251
case ISD::VECREDUCE_FADD:

‎llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -118,6 +118,7 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
118118
case ISD::VP_SRL: Res = PromoteIntRes_SRL(N); break;
119119
case ISD::VP_TRUNCATE:
120120
case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
121+
case ISD::POISON:
121122
case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
122123
case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
123124
case ISD::VSCALE: Res = PromoteIntRes_VSCALE(N); break;
@@ -2840,6 +2841,7 @@ void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
28402841
case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
28412842
case ISD::SELECT: SplitRes_Select(N, Lo, Hi); break;
28422843
case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
2844+
case ISD::POISON:
28432845
case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
28442846
case ISD::FREEZE: SplitRes_FREEZE(N, Lo, Hi); break;
28452847
case ISD::SETCC: ExpandIntRes_SETCC(N, Lo, Hi); break;

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -71,6 +71,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
7171
case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
7272
case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
7373
case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
74+
case ISD::POISON:
7475
case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
7576
case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
7677
case ISD::IS_FPCLASS: R = ScalarizeVecRes_IS_FPCLASS(N); break;
@@ -1117,6 +1118,7 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
11171118
case ISD::VP_MERGE:
11181119
case ISD::VP_SELECT: SplitRes_Select(N, Lo, Hi); break;
11191120
case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1121+
case ISD::POISON:
11201122
case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
11211123
case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
11221124
case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
@@ -4523,6 +4525,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
45234525
case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
45244526
case ISD::VP_SETCC:
45254527
case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
4528+
case ISD::POISON:
45264529
case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
45274530
case ISD::VECTOR_SHUFFLE:
45284531
Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 32 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5458,6 +5458,9 @@ bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison(SDValue Op,
54585458
case ISD::CopyFromReg:
54595459
return true;
54605460

5461+
case ISD::POISON:
5462+
return false;
5463+
54615464
case ISD::UNDEF:
54625465
return PoisonOnly;
54635466

@@ -6310,6 +6313,10 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
63106313
if (OpOpcode == ISD::UNDEF)
63116314
// sext(undef) = 0, because the top bits will all be the same.
63126315
return getConstant(0, DL, VT);
6316+
6317+
if (OpOpcode == ISD::POISON)
6318+
return getPoison(VT);
6319+
63136320
break;
63146321
case ISD::ZERO_EXTEND:
63156322
assert(VT.isInteger() && N1.getValueType().isInteger() &&
@@ -6331,6 +6338,9 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
63316338
// zext(undef) = 0, because the top bits will be zero.
63326339
return getConstant(0, DL, VT);
63336340

6341+
if (OpOpcode == ISD::POISON)
6342+
return getPoison(VT);
6343+
63346344
// Skip unnecessary zext_inreg pattern:
63356345
// (zext (trunc x)) -> x iff the upper bits are known zero.
63366346
// TODO: Remove (zext (trunc (and x, c))) exception which some targets
@@ -6371,6 +6381,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
63716381
}
63726382
if (OpOpcode == ISD::UNDEF)
63736383
return getUNDEF(VT);
6384+
if (OpOpcode == ISD::POISON)
6385+
return getPoison(VT);
63746386

63756387
// (ext (trunc x)) -> x
63766388
if (OpOpcode == ISD::TRUNCATE) {
@@ -6406,6 +6418,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
64066418
}
64076419
if (OpOpcode == ISD::UNDEF)
64086420
return getUNDEF(VT);
6421+
if (OpOpcode == ISD::POISON)
6422+
return getPoison(VT);
64096423
if (OpOpcode == ISD::VSCALE && !NewNodesMustHaveLegalTypes)
64106424
return getVScale(DL, VT,
64116425
N1.getConstantOperandAPInt(0).trunc(VT.getSizeInBits()));
@@ -6424,13 +6438,17 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
64246438
assert(VT.isInteger() && VT == N1.getValueType() && "Invalid ABS!");
64256439
if (OpOpcode == ISD::UNDEF)
64266440
return getConstant(0, DL, VT);
6441+
if (OpOpcode == ISD::POISON)
6442+
return getPoison(VT);
64276443
break;
64286444
case ISD::BSWAP:
64296445
assert(VT.isInteger() && VT == N1.getValueType() && "Invalid BSWAP!");
64306446
assert((VT.getScalarSizeInBits() % 16 == 0) &&
64316447
"BSWAP types must be a multiple of 16 bits!");
64326448
if (OpOpcode == ISD::UNDEF)
64336449
return getUNDEF(VT);
6450+
if (OpOpcode == ISD::POISON)
6451+
return getPoison(VT);
64346452
// bswap(bswap(X)) -> X.
64356453
if (OpOpcode == ISD::BSWAP)
64366454
return N1.getOperand(0);
@@ -6439,6 +6457,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
64396457
assert(VT.isInteger() && VT == N1.getValueType() && "Invalid BITREVERSE!");
64406458
if (OpOpcode == ISD::UNDEF)
64416459
return getUNDEF(VT);
6460+
if (OpOpcode == ISD::POISON)
6461+
return getPoison(VT);
64426462
break;
64436463
case ISD::BITCAST:
64446464
assert(VT.getSizeInBits() == N1.getValueSizeInBits() &&
@@ -6448,6 +6468,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
64486468
return getNode(ISD::BITCAST, DL, VT, N1.getOperand(0));
64496469
if (OpOpcode == ISD::UNDEF)
64506470
return getUNDEF(VT);
6471+
if (OpOpcode == ISD::POISON)
6472+
return getPoison(VT);
64516473
break;
64526474
case ISD::SCALAR_TO_VECTOR:
64536475
assert(VT.isVector() && !N1.getValueType().isVector() &&
@@ -6458,6 +6480,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
64586480
"Illegal SCALAR_TO_VECTOR node!");
64596481
if (OpOpcode == ISD::UNDEF)
64606482
return getUNDEF(VT);
6483+
if (OpOpcode == ISD::POISON)
6484+
return getPoison(VT);
64616485
// scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined.
64626486
if (OpOpcode == ISD::EXTRACT_VECTOR_ELT &&
64636487
isa<ConstantSDNode>(N1.getOperand(1)) &&
@@ -6469,6 +6493,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
64696493
// Negation of an unknown bag of bits is still completely undefined.
64706494
if (OpOpcode == ISD::UNDEF)
64716495
return getUNDEF(VT);
6496+
if (OpOpcode == ISD::POISON)
6497+
return getPoison(VT);
64726498

64736499
if (OpOpcode == ISD::FNEG) // --X -> X
64746500
return N1.getOperand(0);
@@ -9237,6 +9263,11 @@ SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
92379263

92389264
SDVTList VTs = Indexed ?
92399265
getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other);
9266+
9267+
// FixedMe: lower poison to undef.
9268+
if (Ptr.getNode()->isPoison())
9269+
Ptr = getUNDEF(Ptr.getValueType());
9270+
92409271
SDValue Ops[] = { Chain, Ptr, Offset };
92419272
FoldingSetNodeID ID;
92429273
AddNodeIDNode(ID, ISD::LOAD, VTs, Ops);
@@ -13374,7 +13405,7 @@ void BuildVectorSDNode::recastRawBits(bool IsLittleEndian,
1337413405
bool BuildVectorSDNode::isConstant() const {
1337513406
for (const SDValue &Op : op_values()) {
1337613407
unsigned Opc = Op.getOpcode();
13377-
if (Opc != ISD::UNDEF && Opc != ISD::Constant && Opc != ISD::ConstantFP)
13408+
if (!Op.isUndef() && Opc != ISD::Constant && Opc != ISD::ConstantFP)
1337813409
return false;
1337913410
}
1338013411
return true;

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1819,7 +1819,7 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
18191819
return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
18201820

18211821
if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1822-
return DAG.getUNDEF(VT);
1822+
return isa<PoisonValue>(C) ? DAG.getPoison(VT) : DAG.getUNDEF(VT);
18231823

18241824
if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
18251825
visit(CE->getOpcode(), *CE);

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -188,6 +188,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
188188
case ISD::CopyToReg: return "CopyToReg";
189189
case ISD::CopyFromReg: return "CopyFromReg";
190190
case ISD::UNDEF: return "undef";
191+
case ISD::POISON: return "poison";
191192
case ISD::VSCALE: return "vscale";
192193
case ISD::MERGE_VALUES: return "merge_values";
193194
case ISD::INLINEASM: return "inlineasm";

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3275,6 +3275,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
32753275
case ISD::WRITE_REGISTER:
32763276
Select_WRITE_REGISTER(NodeToMatch);
32773277
return;
3278+
case ISD::POISON:
32783279
case ISD::UNDEF:
32793280
Select_UNDEF(NodeToMatch);
32803281
return;

‎llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -27,14 +27,6 @@ define signext i32 @foo() #1 personality ptr @__gxx_personality_v0 {
2727
; CHECK-NEXT: .cfi_remember_state
2828
; CHECK-NEXT: .Ltmp0:
2929
; CHECK-NEXT: addi sp, sp, -32
30-
; CHECK-NEXT: li a0, 0
31-
; CHECK-NEXT: li a1, 0
32-
; CHECK-NEXT: li a2, 0
33-
; CHECK-NEXT: li a3, 0
34-
; CHECK-NEXT: li a4, 0
35-
; CHECK-NEXT: li a5, 0
36-
; CHECK-NEXT: li a6, 0
37-
; CHECK-NEXT: li a7, 0
3830
; CHECK-NEXT: call _Z3fooiiiiiiiiiiPi
3931
; CHECK-NEXT: addi sp, sp, 32
4032
; CHECK-NEXT: .Ltmp1:

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