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Explicitly set PartialReduceMLAActions
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llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

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@@ -1604,6 +1604,26 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::MSTORE, VT, Custom);
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}
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if (EnablePartialReduceNodes) {
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for (MVT VT : MVT::integer_scalable_vector_valuetypes()) {
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for (MVT InnerVT : MVT::integer_scalable_vector_valuetypes()) {
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// 1. Set all combinations where a type is illegal to "Legal"
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// - These will be legalized to a legal type pair
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// - Avoid expanding them too early (or preventing folds)
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if (!isTypeLegal(VT) || !isTypeLegal(InnerVT)) {
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setPartialReduceMLAAction(VT, InnerVT, Legal);
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continue;
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}
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// 2. Set all legal combinations to "Expand"
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// - Not all of these can be lowered (via a Legal or Custom lowering).
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setPartialReduceMLAAction(VT, InnerVT, Expand);
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}
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}
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// 3. Mark known legal pairs as 'Legal' (these will expand to USDOT).
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setPartialReduceMLAAction(MVT::nxv2i64, MVT::nxv8i16, Legal);
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setPartialReduceMLAAction(MVT::nxv4i32, MVT::nxv16i8, Legal);
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}
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// Firstly, exclude all scalable vector extending loads/truncating stores,
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// include both integer and floating scalable vector.
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for (MVT VT : MVT::scalable_vector_valuetypes()) {
@@ -1856,6 +1876,14 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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// Other pairs will default to 'Expand'.
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setPartialReduceMLAAction(MVT::nxv2i64, MVT::nxv8i16, Legal);
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setPartialReduceMLAAction(MVT::nxv4i32, MVT::nxv16i8, Legal);
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setPartialReduceMLAAction(MVT::nxv2i64, MVT::nxv8i64, Custom);
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setPartialReduceMLAAction(MVT::nxv4i32, MVT::nxv16i32, Custom);
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setPartialReduceMLAAction(MVT::nxv2i64, MVT::nxv4i64, Custom);
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setPartialReduceMLAAction(MVT::nxv4i32, MVT::nxv8i32, Custom);
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setPartialReduceMLAAction(MVT::nxv8i16, MVT::nxv16i16, Custom);
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setPartialReduceMLAAction(MVT::nxv16i8, MVT::nxv32i8, Custom);
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}
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// Handle operations that are only available in non-streaming SVE mode.

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