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[CodeGen] Make use of MachineInstr::all_defs and all_uses. NFCI.
Differential Revision: https://reviews.llvm.org/D151424
1 parent 2de54b9 commit 5022fc2

29 files changed

+119
-169
lines changed

‎llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -351,8 +351,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(
351351
// dead, or because only a subregister is live at the def. If we
352352
// don't do this the dead def will be incorrectly merged into the
353353
// previous def.
354-
for (const MachineOperand &MO : MI.operands()) {
355-
if (!MO.isReg() || !MO.isDef()) continue;
354+
for (const MachineOperand &MO : MI.all_defs()) {
356355
Register Reg = MO.getReg();
357356
if (Reg == 0) continue;
358357

‎llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -707,8 +707,8 @@ static void interpretValues(const MachineInstr *CurMI,
707707
if (MI.isDebugInstr())
708708
return;
709709

710-
for (const MachineOperand &MO : MI.operands()) {
711-
if (MO.isReg() && MO.isDef() && MO.getReg().isPhysical()) {
710+
for (const MachineOperand &MO : MI.all_defs()) {
711+
if (MO.getReg().isPhysical()) {
712712
for (auto &FwdReg : ForwardedRegWorklist)
713713
if (TRI.regsOverlap(FwdReg.first, MO.getReg()))
714714
Defs.insert(FwdReg.first);

‎llvm/lib/CodeGen/BranchFolding.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1997,8 +1997,8 @@ bool BranchFolder::HoistCommonCodeInSuccs(MachineBasicBlock *MBB) {
19971997
break;
19981998

19991999
// Remove kills from ActiveDefsSet, these registers had short live ranges.
2000-
for (const MachineOperand &MO : TIB->operands()) {
2001-
if (!MO.isReg() || !MO.isUse() || !MO.isKill())
2000+
for (const MachineOperand &MO : TIB->all_uses()) {
2001+
if (!MO.isKill())
20022002
continue;
20032003
Register Reg = MO.getReg();
20042004
if (!Reg)
@@ -2015,8 +2015,8 @@ bool BranchFolder::HoistCommonCodeInSuccs(MachineBasicBlock *MBB) {
20152015
}
20162016

20172017
// Track local defs so we can update liveins.
2018-
for (const MachineOperand &MO : TIB->operands()) {
2019-
if (!MO.isReg() || !MO.isDef() || MO.isDead())
2018+
for (const MachineOperand &MO : TIB->all_defs()) {
2019+
if (MO.isDead())
20202020
continue;
20212021
Register Reg = MO.getReg();
20222022
if (!Reg || Reg.isVirtual())

‎llvm/lib/CodeGen/BreakFalseDeps.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -140,9 +140,8 @@ bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
140140

141141
// If the instruction has a true dependency, we can hide the false depdency
142142
// behind it.
143-
for (MachineOperand &CurrMO : MI->operands()) {
144-
if (!CurrMO.isReg() || CurrMO.isDef() || CurrMO.isUndef() ||
145-
!OpRC->contains(CurrMO.getReg()))
143+
for (MachineOperand &CurrMO : MI->all_uses()) {
144+
if (CurrMO.isUndef() || !OpRC->contains(CurrMO.getReg()))
146145
continue;
147146
// We found a true dependency - replace the undef register with the true
148147
// dependency.

‎llvm/lib/CodeGen/DeadMachineInstructionElim.cpp

Lines changed: 17 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -75,27 +75,25 @@ bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
7575
return false;
7676

7777
// Examine each operand.
78-
for (const MachineOperand &MO : MI->operands()) {
79-
if (MO.isReg() && MO.isDef()) {
80-
Register Reg = MO.getReg();
81-
if (Reg.isPhysical()) {
82-
// Don't delete live physreg defs, or any reserved register defs.
83-
if (!LivePhysRegs.available(Reg) || MRI->isReserved(Reg))
84-
return false;
85-
} else {
86-
if (MO.isDead()) {
78+
for (const MachineOperand &MO : MI->all_defs()) {
79+
Register Reg = MO.getReg();
80+
if (Reg.isPhysical()) {
81+
// Don't delete live physreg defs, or any reserved register defs.
82+
if (!LivePhysRegs.available(Reg) || MRI->isReserved(Reg))
83+
return false;
84+
} else {
85+
if (MO.isDead()) {
8786
#ifndef NDEBUG
88-
// Basic check on the register. All of them should be 'undef'.
89-
for (auto &U : MRI->use_nodbg_operands(Reg))
90-
assert(U.isUndef() && "'Undef' use on a 'dead' register is found!");
87+
// Basic check on the register. All of them should be 'undef'.
88+
for (auto &U : MRI->use_nodbg_operands(Reg))
89+
assert(U.isUndef() && "'Undef' use on a 'dead' register is found!");
9190
#endif
92-
continue;
93-
}
94-
for (const MachineInstr &Use : MRI->use_nodbg_instructions(Reg)) {
95-
if (&Use != MI)
96-
// This def has a non-debug use. Don't delete the instruction!
97-
return false;
98-
}
91+
continue;
92+
}
93+
for (const MachineInstr &Use : MRI->use_nodbg_instructions(Reg)) {
94+
if (&Use != MI)
95+
// This def has a non-debug use. Don't delete the instruction!
96+
return false;
9997
}
10098
}
10199
}

‎llvm/lib/CodeGen/GlobalISel/Utils.cpp

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -230,10 +230,7 @@ bool llvm::isTriviallyDead(const MachineInstr &MI,
230230
return false;
231231

232232
// Instructions without side-effects are dead iff they only define dead vregs.
233-
for (const auto &MO : MI.operands()) {
234-
if (!MO.isReg() || !MO.isDef())
235-
continue;
236-
233+
for (const auto &MO : MI.all_defs()) {
237234
Register Reg = MO.getReg();
238235
if (Reg.isPhysical() || !MRI.use_nodbg_empty(Reg))
239236
return false;

‎llvm/lib/CodeGen/ImplicitNullChecks.cpp

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -778,18 +778,16 @@ void ImplicitNullChecks::rewriteNullChecks(
778778
// The original operation may define implicit-defs alongside
779779
// the value.
780780
MachineBasicBlock *MBB = NC.getMemOperation()->getParent();
781-
for (const MachineOperand &MO : FaultingInstr->operands()) {
782-
if (!MO.isReg() || !MO.isDef())
783-
continue;
781+
for (const MachineOperand &MO : FaultingInstr->all_defs()) {
784782
Register Reg = MO.getReg();
785783
if (!Reg || MBB->isLiveIn(Reg))
786784
continue;
787785
MBB->addLiveIn(Reg);
788786
}
789787

790788
if (auto *DepMI = NC.getOnlyDependency()) {
791-
for (auto &MO : DepMI->operands()) {
792-
if (!MO.isReg() || !MO.getReg() || !MO.isDef() || MO.isDead())
789+
for (auto &MO : DepMI->all_defs()) {
790+
if (!MO.getReg() || MO.isDead())
793791
continue;
794792
if (!NC.getNotNullSucc()->isLiveIn(MO.getReg()))
795793
NC.getNotNullSucc()->addLiveIn(MO.getReg());

‎llvm/lib/CodeGen/InlineSpiller.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -268,8 +268,8 @@ static Register isFullCopyOf(const MachineInstr &MI, Register Reg) {
268268
}
269269

270270
static void getVDefInterval(const MachineInstr &MI, LiveIntervals &LIS) {
271-
for (const MachineOperand &MO : MI.operands())
272-
if (MO.isReg() && MO.isDef() && MO.getReg().isVirtual())
271+
for (const MachineOperand &MO : MI.all_defs())
272+
if (MO.getReg().isVirtual())
273273
LIS.getInterval(MO.getReg());
274274
}
275275

@@ -593,8 +593,8 @@ bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) {
593593

594594
if (!ParentVNI) {
595595
LLVM_DEBUG(dbgs() << "\tadding <undef> flags: ");
596-
for (MachineOperand &MO : MI.operands())
597-
if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg())
596+
for (MachineOperand &MO : MI.all_uses())
597+
if (MO.getReg() == VirtReg.reg())
598598
MO.setIsUndef();
599599
LLVM_DEBUG(dbgs() << UseIdx << '\t' << MI);
600600
return true;

‎llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2162,8 +2162,8 @@ bool VarLocBasedLDV::isEntryValueCandidate(
21622162
/// Collect all register defines (including aliases) for the given instruction.
21632163
static void collectRegDefs(const MachineInstr &MI, DefinedRegsSet &Regs,
21642164
const TargetRegisterInfo *TRI) {
2165-
for (const MachineOperand &MO : MI.operands()) {
2166-
if (MO.isReg() && MO.isDef() && MO.getReg() && MO.getReg().isPhysical()) {
2165+
for (const MachineOperand &MO : MI.all_defs()) {
2166+
if (MO.getReg() && MO.getReg().isPhysical()) {
21672167
Regs.insert(MO.getReg());
21682168
for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)
21692169
Regs.insert(*AI);

‎llvm/lib/CodeGen/LiveVariables.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -207,8 +207,8 @@ LiveVariables::FindLastPartialDef(Register Reg,
207207
return nullptr;
208208

209209
PartDefRegs.insert(LastDefReg);
210-
for (MachineOperand &MO : LastDef->operands()) {
211-
if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
210+
for (MachineOperand &MO : LastDef->all_defs()) {
211+
if (MO.getReg() == 0)
212212
continue;
213213
Register DefReg = MO.getReg();
214214
if (TRI->isSubRegister(Reg, DefReg)) {

‎llvm/lib/CodeGen/MachineBasicBlock.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1130,9 +1130,8 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(
11301130
if (LV)
11311131
for (MachineInstr &MI :
11321132
llvm::make_range(getFirstInstrTerminator(), instr_end())) {
1133-
for (MachineOperand &MO : MI.operands()) {
1134-
if (!MO.isReg() || MO.getReg() == 0 || !MO.isUse() || !MO.isKill() ||
1135-
MO.isUndef())
1133+
for (MachineOperand &MO : MI.all_uses()) {
1134+
if (MO.getReg() == 0 || !MO.isKill() || MO.isUndef())
11361135
continue;
11371136
Register Reg = MO.getReg();
11381137
if (Reg.isPhysical() || LV->getVarInfo(Reg).removeKill(MI)) {

‎llvm/lib/CodeGen/MachineCSE.cpp

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -175,9 +175,7 @@ INITIALIZE_PASS_END(MachineCSE, DEBUG_TYPE,
175175
bool MachineCSE::PerformTrivialCopyPropagation(MachineInstr *MI,
176176
MachineBasicBlock *MBB) {
177177
bool Changed = false;
178-
for (MachineOperand &MO : MI->operands()) {
179-
if (!MO.isReg() || !MO.isUse())
180-
continue;
178+
for (MachineOperand &MO : MI->all_uses()) {
181179
Register Reg = MO.getReg();
182180
if (!Reg.isVirtual())
183181
continue;
@@ -291,9 +289,7 @@ bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
291289
PhysDefVector &PhysDefs,
292290
bool &PhysUseDef) const {
293291
// First, add all uses to PhysRefs.
294-
for (const MachineOperand &MO : MI->operands()) {
295-
if (!MO.isReg() || MO.isDef())
296-
continue;
292+
for (const MachineOperand &MO : MI->all_uses()) {
297293
Register Reg = MO.getReg();
298294
if (!Reg)
299295
continue;
@@ -483,8 +479,8 @@ bool MachineCSE::isProfitableToCSE(Register CSReg, Register Reg,
483479
// Heuristics #2: If the expression doesn't not use a vr and the only use
484480
// of the redundant computation are copies, do not cse.
485481
bool HasVRegUse = false;
486-
for (const MachineOperand &MO : MI->operands()) {
487-
if (MO.isReg() && MO.isUse() && MO.getReg().isVirtual()) {
482+
for (const MachineOperand &MO : MI->all_uses()) {
483+
if (MO.getReg().isVirtual()) {
488484
HasVRegUse = true;
489485
break;
490486
}

‎llvm/lib/CodeGen/MachineCombiner.cpp

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -217,11 +217,9 @@ MachineCombiner::getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
217217
// are tracked in the InstrIdxForVirtReg map depth is looked up in InstrDepth
218218
for (auto *InstrPtr : InsInstrs) { // for each Use
219219
unsigned IDepth = 0;
220-
for (const MachineOperand &MO : InstrPtr->operands()) {
220+
for (const MachineOperand &MO : InstrPtr->all_uses()) {
221221
// Check for virtual register operand.
222-
if (!(MO.isReg() && MO.getReg().isVirtual()))
223-
continue;
224-
if (!MO.isUse())
222+
if (!MO.getReg().isVirtual())
225223
continue;
226224
unsigned DepthOp = 0;
227225
unsigned LatencyOp = 0;
@@ -272,11 +270,9 @@ unsigned MachineCombiner::getLatency(MachineInstr *Root, MachineInstr *NewRoot,
272270
// Check each definition in NewRoot and compute the latency
273271
unsigned NewRootLatency = 0;
274272

275-
for (const MachineOperand &MO : NewRoot->operands()) {
273+
for (const MachineOperand &MO : NewRoot->all_defs()) {
276274
// Check for virtual register operand.
277-
if (!(MO.isReg() && MO.getReg().isVirtual()))
278-
continue;
279-
if (!MO.isDef())
275+
if (!MO.getReg().isVirtual())
280276
continue;
281277
// Get the first instruction that uses MO
282278
MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(MO.getReg());

‎llvm/lib/CodeGen/MachineDebugify.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -116,8 +116,8 @@ bool applyDebugifyMetadataToMachineFunction(MachineModuleInfo &MMI,
116116

117117
// Emit DBG_VALUEs for register definitions.
118118
SmallVector<MachineOperand *, 4> RegDefs;
119-
for (MachineOperand &MO : MI.operands())
120-
if (MO.isReg() && MO.isDef() && MO.getReg())
119+
for (MachineOperand &MO : MI.all_defs())
120+
if (MO.getReg())
121121
RegDefs.push_back(&MO);
122122
for (MachineOperand *MO : RegDefs)
123123
BuildMI(MBB, InsertBeforeIt, MI.getDebugLoc(), DbgValDesc,

‎llvm/lib/CodeGen/MachineFunction.cpp

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1082,8 +1082,8 @@ auto MachineFunction::salvageCopySSAImpl(MachineInstr &MI)
10821082
if (State.first.isVirtual()) {
10831083
// Virtual register def -- we can just look up where this happens.
10841084
MachineInstr *Inst = MRI.def_begin(State.first)->getParent();
1085-
for (auto &MO : Inst->operands()) {
1086-
if (!MO.isReg() || !MO.isDef() || MO.getReg() != State.first)
1085+
for (auto &MO : Inst->all_defs()) {
1086+
if (MO.getReg() != State.first)
10871087
continue;
10881088
return ApplySubregisters({Inst->getDebugInstrNum(), MO.getOperandNo()});
10891089
}
@@ -1100,10 +1100,9 @@ auto MachineFunction::salvageCopySSAImpl(MachineInstr &MI)
11001100
auto RMII = CurInst->getReverseIterator();
11011101
auto PrevInstrs = make_range(RMII, CurInst->getParent()->instr_rend());
11021102
for (auto &ToExamine : PrevInstrs) {
1103-
for (auto &MO : ToExamine.operands()) {
1103+
for (auto &MO : ToExamine.all_defs()) {
11041104
// Test for operand that defines something aliasing RegToSeek.
1105-
if (!MO.isReg() || !MO.isDef() ||
1106-
!TRI.regsOverlap(RegToSeek, MO.getReg()))
1105+
if (!TRI.regsOverlap(RegToSeek, MO.getReg()))
11071106
continue;
11081107

11091108
return ApplySubregisters(

‎llvm/lib/CodeGen/MachineLICM.cpp

Lines changed: 10 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -575,8 +575,8 @@ void MachineLICMBase::HoistRegionPostRA() {
575575
if (!PhysRegClobbers.test(Def) && !TermRegs.test(Def)) {
576576
bool Safe = true;
577577
MachineInstr *MI = Candidate.MI;
578-
for (const MachineOperand &MO : MI->operands()) {
579-
if (!MO.isReg() || MO.isDef() || !MO.getReg())
578+
for (const MachineOperand &MO : MI->all_uses()) {
579+
if (!MO.getReg())
580580
continue;
581581
Register Reg = MO.getReg();
582582
if (PhysRegDefs.test(Reg) ||
@@ -600,8 +600,9 @@ void MachineLICMBase::AddToLiveIns(MCRegister Reg) {
600600
if (!BB->isLiveIn(Reg))
601601
BB->addLiveIn(Reg);
602602
for (MachineInstr &MI : *BB) {
603-
for (MachineOperand &MO : MI.operands()) {
604-
if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue;
603+
for (MachineOperand &MO : MI.all_uses()) {
604+
if (!MO.getReg())
605+
continue;
605606
if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg()))
606607
MO.setIsKill(false);
607608
}
@@ -669,8 +670,8 @@ bool MachineLICMBase::isTriviallyReMaterializable(
669670
if (!TII->isTriviallyReMaterializable(MI))
670671
return false;
671672

672-
for (const MachineOperand &MO : MI.operands()) {
673-
if (MO.isReg() && MO.isUse() && MO.getReg().isVirtual())
673+
for (const MachineOperand &MO : MI.all_uses()) {
674+
if (MO.getReg().isVirtual())
674675
return false;
675676
}
676677

@@ -1014,9 +1015,7 @@ bool MachineLICMBase::HasLoopPHIUse(const MachineInstr *MI) const {
10141015
SmallVector<const MachineInstr*, 8> Work(1, MI);
10151016
do {
10161017
MI = Work.pop_back_val();
1017-
for (const MachineOperand &MO : MI->operands()) {
1018-
if (!MO.isReg() || !MO.isDef())
1019-
continue;
1018+
for (const MachineOperand &MO : MI->all_defs()) {
10201019
Register Reg = MO.getReg();
10211020
if (!Reg.isVirtual())
10221021
continue;
@@ -1455,8 +1454,8 @@ bool MachineLICMBase::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader) {
14551454
// Clear the kill flags of any register this instruction defines,
14561455
// since they may need to be live throughout the entire loop
14571456
// rather than just live for part of it.
1458-
for (MachineOperand &MO : MI->operands())
1459-
if (MO.isReg() && MO.isDef() && !MO.isDead())
1457+
for (MachineOperand &MO : MI->all_defs())
1458+
if (!MO.isDead())
14601459
MRI->clearKillFlags(MO.getReg());
14611460

14621461
// Add to the CSE map.

‎llvm/lib/CodeGen/MachinePipeliner.cpp

Lines changed: 12 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1557,20 +1557,19 @@ static void computeLiveOuts(MachineFunction &MF, RegPressureTracker &RPTracker,
15571557
const MachineInstr *MI = SU->getInstr();
15581558
if (MI->isPHI())
15591559
continue;
1560-
for (const MachineOperand &MO : MI->operands())
1561-
if (MO.isReg() && MO.isUse()) {
1562-
Register Reg = MO.getReg();
1563-
if (Reg.isVirtual())
1564-
Uses.insert(Reg);
1565-
else if (MRI.isAllocatable(Reg))
1566-
for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
1567-
++Units)
1568-
Uses.insert(*Units);
1569-
}
1560+
for (const MachineOperand &MO : MI->all_uses()) {
1561+
Register Reg = MO.getReg();
1562+
if (Reg.isVirtual())
1563+
Uses.insert(Reg);
1564+
else if (MRI.isAllocatable(Reg))
1565+
for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
1566+
++Units)
1567+
Uses.insert(*Units);
1568+
}
15701569
}
15711570
for (SUnit *SU : NS)
1572-
for (const MachineOperand &MO : SU->getInstr()->operands())
1573-
if (MO.isReg() && MO.isDef() && !MO.isDead()) {
1571+
for (const MachineOperand &MO : SU->getInstr()->all_defs())
1572+
if (!MO.isDead()) {
15741573
Register Reg = MO.getReg();
15751574
if (Reg.isVirtual()) {
15761575
if (!Uses.count(Reg))
@@ -2652,9 +2651,7 @@ bool SMSchedule::isLoopCarriedDefOfUse(SwingSchedulerDAG *SSD,
26522651
if (!isLoopCarried(SSD, *Phi))
26532652
return false;
26542653
unsigned LoopReg = getLoopPhiReg(*Phi, Phi->getParent());
2655-
for (MachineOperand &DMO : Def->operands()) {
2656-
if (!DMO.isReg() || !DMO.isDef())
2657-
continue;
2654+
for (MachineOperand &DMO : Def->all_defs()) {
26582655
if (DMO.getReg() == LoopReg)
26592656
return true;
26602657
}

‎llvm/lib/CodeGen/MachineSSAContext.cpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -42,10 +42,8 @@ void MachineSSAContext::appendBlockTerms(
4242
void MachineSSAContext::appendBlockDefs(SmallVectorImpl<Register> &defs,
4343
const MachineBasicBlock &block) {
4444
for (const MachineInstr &instr : block.instrs()) {
45-
for (const MachineOperand &op : instr.operands()) {
46-
if (op.isReg() && op.isDef())
47-
defs.push_back(op.getReg());
48-
}
45+
for (const MachineOperand &op : instr.all_defs())
46+
defs.push_back(op.getReg());
4947
}
5048
}
5149

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