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Move to target DAG-combine
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-95
lines changed

7 files changed

+123
-95
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‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1140,6 +1140,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
11401140

11411141
setTargetDAGCombine(ISD::SCALAR_TO_VECTOR);
11421142

1143+
setTargetDAGCombine(ISD::SHL);
1144+
11431145
// In case of strict alignment, avoid an excessive number of byte wide stores.
11441146
MaxStoresPerMemsetOptSize = 8;
11451147
MaxStoresPerMemset =
@@ -26365,6 +26367,36 @@ performScalarToVectorCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
2636526367
return NVCAST;
2636626368
}
2636726369

26370+
static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG) {
26371+
SDValue Op0 = N->getOperand(0);
26372+
SDValue Op1 = N->getOperand(1);
26373+
EVT VT = N->getValueType(0);
26374+
if (VT != MVT::i32 && VT != MVT::i64)
26375+
return SDValue();
26376+
26377+
// If the operand is a bitwise AND with a constant RHS, and the shift is the
26378+
// only use, we can pull it out of the shift.
26379+
//
26380+
// (shl (and X, C1), C2) -> (and (shl X, C2), (shl C1, C2))
26381+
if (!Op0.hasOneUse() || Op0.getOpcode() != ISD::AND)
26382+
return SDValue();
26383+
26384+
ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(Op0.getOperand(1));
26385+
ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(Op1);
26386+
if (!C1 || !C2)
26387+
return SDValue();
26388+
26389+
// Might be folded into shifted add/sub, do not lower.
26390+
if (N->hasOneUse() && (N->use_begin()->getOpcode() == ISD::ADD ||
26391+
N->use_begin()->getOpcode() == ISD::SUB))
26392+
return SDValue();
26393+
26394+
SDLoc DL(N);
26395+
SDValue NewRHS = DAG.getNode(ISD::SHL, DL, VT, Op0.getOperand(1), Op1);
26396+
SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, Op0->getOperand(0), Op1);
26397+
return DAG.getNode(ISD::AND, DL, VT, NewShift, NewRHS);
26398+
}
26399+
2636826400
SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
2636926401
DAGCombinerInfo &DCI) const {
2637026402
SelectionDAG &DAG = DCI.DAG;
@@ -26710,6 +26742,8 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
2671026742
return performCTLZCombine(N, DAG, Subtarget);
2671126743
case ISD::SCALAR_TO_VECTOR:
2671226744
return performScalarToVectorCombine(N, DCI, DAG);
26745+
case ISD::SHL:
26746+
return performSHLCombine(N, DAG);
2671326747
}
2671426748
return SDValue();
2671526749
}

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -8968,15 +8968,6 @@ def : Pat<(shl (i64 (zext GPR32:$Rn)), (i64 imm0_63:$imm)),
89688968
(i64 (i64shift_a imm0_63:$imm)),
89698969
(i64 (i64shift_sext_i32 imm0_63:$imm)))>;
89708970

8971-
def : Pat<(shl (i64 (and (i64 (anyext GPR32:$Rn)), 0xff)), (i64 imm0_63:$imm)),
8972-
(UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
8973-
(i64 (i64shift_a imm0_63:$imm)),
8974-
(i64 (i64shift_sext_i8 imm0_63:$imm)))>;
8975-
def : Pat<(shl (i64 (and (i64 (anyext GPR32:$Rn)), 0xffff)), (i64 imm0_63:$imm)),
8976-
(UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
8977-
(i64 (i64shift_a imm0_63:$imm)),
8978-
(i64 (i64shift_sext_i16 imm0_63:$imm)))>;
8979-
89808971
// sra patterns have an AddedComplexity of 10, so make sure we have a higher
89818972
// AddedComplexity for the following patterns since we want to match sext + sra
89828973
// patterns before we attempt to match a single sra node.

‎llvm/test/CodeGen/AArch64/aarch64-fold-lslfast.ll

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -13,10 +13,11 @@ define i16 @halfword(ptr %ctx, i32 %xor72) nounwind {
1313
; CHECK0-SDAG-LABEL: halfword:
1414
; CHECK0-SDAG: // %bb.0:
1515
; CHECK0-SDAG-NEXT: stp x30, x21, [sp, #-32]! // 16-byte Folded Spill
16-
; CHECK0-SDAG-NEXT: lsr w8, w1, #9
16+
; CHECK0-SDAG-NEXT: // kill: def $w1 killed $w1 def $x1
17+
; CHECK0-SDAG-NEXT: ubfx x8, x1, #9, #8
1718
; CHECK0-SDAG-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
1819
; CHECK0-SDAG-NEXT: mov x19, x0
19-
; CHECK0-SDAG-NEXT: ubfiz x21, x8, #1, #8
20+
; CHECK0-SDAG-NEXT: lsl x21, x8, #1
2021
; CHECK0-SDAG-NEXT: ldrh w20, [x0, x21]
2122
; CHECK0-SDAG-NEXT: bl foo
2223
; CHECK0-SDAG-NEXT: mov w0, w20
@@ -230,9 +231,10 @@ define i16 @multi_use_half_word(ptr %ctx, i32 %xor72) {
230231
; CHECK0-SDAG-NEXT: .cfi_offset w21, -24
231232
; CHECK0-SDAG-NEXT: .cfi_offset w22, -32
232233
; CHECK0-SDAG-NEXT: .cfi_offset w30, -48
233-
; CHECK0-SDAG-NEXT: lsr w8, w1, #9
234+
; CHECK0-SDAG-NEXT: // kill: def $w1 killed $w1 def $x1
235+
; CHECK0-SDAG-NEXT: ubfx x8, x1, #9, #8
234236
; CHECK0-SDAG-NEXT: mov x19, x0
235-
; CHECK0-SDAG-NEXT: ubfiz x21, x8, #1, #8
237+
; CHECK0-SDAG-NEXT: lsl x21, x8, #1
236238
; CHECK0-SDAG-NEXT: ldrh w20, [x0, x21]
237239
; CHECK0-SDAG-NEXT: add w22, w20, #1
238240
; CHECK0-SDAG-NEXT: bl foo

‎llvm/test/CodeGen/AArch64/const-shift-of-constmasked.ll

Lines changed: 47 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -190,8 +190,7 @@ define i8 @test_i8_224_mask_ashr_6(i8 %a0) {
190190
define i8 @test_i8_7_mask_shl_1(i8 %a0) {
191191
; CHECK-LABEL: test_i8_7_mask_shl_1:
192192
; CHECK: // %bb.0:
193-
; CHECK-NEXT: and w8, w0, #0x7
194-
; CHECK-NEXT: lsl w0, w8, #1
193+
; CHECK-NEXT: ubfiz w0, w0, #1, #3
195194
; CHECK-NEXT: ret
196195
%t0 = and i8 %a0, 7
197196
%t1 = shl i8 %t0, 1
@@ -200,8 +199,7 @@ define i8 @test_i8_7_mask_shl_1(i8 %a0) {
200199
define i8 @test_i8_7_mask_shl_4(i8 %a0) {
201200
; CHECK-LABEL: test_i8_7_mask_shl_4:
202201
; CHECK: // %bb.0:
203-
; CHECK-NEXT: and w8, w0, #0x7
204-
; CHECK-NEXT: lsl w0, w8, #4
202+
; CHECK-NEXT: ubfiz w0, w0, #4, #3
205203
; CHECK-NEXT: ret
206204
%t0 = and i8 %a0, 7
207205
%t1 = shl i8 %t0, 4
@@ -229,8 +227,8 @@ define i8 @test_i8_7_mask_shl_6(i8 %a0) {
229227
define i8 @test_i8_28_mask_shl_1(i8 %a0) {
230228
; CHECK-LABEL: test_i8_28_mask_shl_1:
231229
; CHECK: // %bb.0:
232-
; CHECK-NEXT: and w8, w0, #0x1c
233-
; CHECK-NEXT: lsl w0, w8, #1
230+
; CHECK-NEXT: lsl w8, w0, #1
231+
; CHECK-NEXT: and w0, w8, #0x38
234232
; CHECK-NEXT: ret
235233
%t0 = and i8 %a0, 28
236234
%t1 = shl i8 %t0, 1
@@ -239,8 +237,8 @@ define i8 @test_i8_28_mask_shl_1(i8 %a0) {
239237
define i8 @test_i8_28_mask_shl_2(i8 %a0) {
240238
; CHECK-LABEL: test_i8_28_mask_shl_2:
241239
; CHECK: // %bb.0:
242-
; CHECK-NEXT: and w8, w0, #0x1c
243-
; CHECK-NEXT: lsl w0, w8, #2
240+
; CHECK-NEXT: lsl w8, w0, #2
241+
; CHECK-NEXT: and w0, w8, #0x70
244242
; CHECK-NEXT: ret
245243
%t0 = and i8 %a0, 28
246244
%t1 = shl i8 %t0, 2
@@ -249,8 +247,8 @@ define i8 @test_i8_28_mask_shl_2(i8 %a0) {
249247
define i8 @test_i8_28_mask_shl_3(i8 %a0) {
250248
; CHECK-LABEL: test_i8_28_mask_shl_3:
251249
; CHECK: // %bb.0:
252-
; CHECK-NEXT: and w8, w0, #0x1c
253-
; CHECK-NEXT: lsl w0, w8, #3
250+
; CHECK-NEXT: lsl w8, w0, #3
251+
; CHECK-NEXT: and w0, w8, #0xe0
254252
; CHECK-NEXT: ret
255253
%t0 = and i8 %a0, 28
256254
%t1 = shl i8 %t0, 3
@@ -259,8 +257,8 @@ define i8 @test_i8_28_mask_shl_3(i8 %a0) {
259257
define i8 @test_i8_28_mask_shl_4(i8 %a0) {
260258
; CHECK-LABEL: test_i8_28_mask_shl_4:
261259
; CHECK: // %bb.0:
262-
; CHECK-NEXT: and w8, w0, #0xc
263-
; CHECK-NEXT: lsl w0, w8, #4
260+
; CHECK-NEXT: lsl w8, w0, #4
261+
; CHECK-NEXT: and w0, w8, #0xc0
264262
; CHECK-NEXT: ret
265263
%t0 = and i8 %a0, 28
266264
%t1 = shl i8 %t0, 4
@@ -270,8 +268,8 @@ define i8 @test_i8_28_mask_shl_4(i8 %a0) {
270268
define i8 @test_i8_224_mask_shl_1(i8 %a0) {
271269
; CHECK-LABEL: test_i8_224_mask_shl_1:
272270
; CHECK: // %bb.0:
273-
; CHECK-NEXT: and w8, w0, #0x60
274-
; CHECK-NEXT: lsl w0, w8, #1
271+
; CHECK-NEXT: lsl w8, w0, #1
272+
; CHECK-NEXT: and w0, w8, #0xc0
275273
; CHECK-NEXT: ret
276274
%t0 = and i8 %a0, 224
277275
%t1 = shl i8 %t0, 1
@@ -465,8 +463,7 @@ define i16 @test_i16_65024_mask_ashr_10(i16 %a0) {
465463
define i16 @test_i16_127_mask_shl_1(i16 %a0) {
466464
; CHECK-LABEL: test_i16_127_mask_shl_1:
467465
; CHECK: // %bb.0:
468-
; CHECK-NEXT: and w8, w0, #0x7f
469-
; CHECK-NEXT: lsl w0, w8, #1
466+
; CHECK-NEXT: ubfiz w0, w0, #1, #7
470467
; CHECK-NEXT: ret
471468
%t0 = and i16 %a0, 127
472469
%t1 = shl i16 %t0, 1
@@ -475,8 +472,7 @@ define i16 @test_i16_127_mask_shl_1(i16 %a0) {
475472
define i16 @test_i16_127_mask_shl_8(i16 %a0) {
476473
; CHECK-LABEL: test_i16_127_mask_shl_8:
477474
; CHECK: // %bb.0:
478-
; CHECK-NEXT: and w8, w0, #0x7f
479-
; CHECK-NEXT: lsl w0, w8, #8
475+
; CHECK-NEXT: ubfiz w0, w0, #8, #7
480476
; CHECK-NEXT: ret
481477
%t0 = and i16 %a0, 127
482478
%t1 = shl i16 %t0, 8
@@ -504,8 +500,8 @@ define i16 @test_i16_127_mask_shl_10(i16 %a0) {
504500
define i16 @test_i16_2032_mask_shl_3(i16 %a0) {
505501
; CHECK-LABEL: test_i16_2032_mask_shl_3:
506502
; CHECK: // %bb.0:
507-
; CHECK-NEXT: and w8, w0, #0x7f0
508-
; CHECK-NEXT: lsl w0, w8, #3
503+
; CHECK-NEXT: lsl w8, w0, #3
504+
; CHECK-NEXT: and w0, w8, #0x3f80
509505
; CHECK-NEXT: ret
510506
%t0 = and i16 %a0, 2032
511507
%t1 = shl i16 %t0, 3
@@ -514,8 +510,8 @@ define i16 @test_i16_2032_mask_shl_3(i16 %a0) {
514510
define i16 @test_i16_2032_mask_shl_4(i16 %a0) {
515511
; CHECK-LABEL: test_i16_2032_mask_shl_4:
516512
; CHECK: // %bb.0:
517-
; CHECK-NEXT: and w8, w0, #0x7f0
518-
; CHECK-NEXT: lsl w0, w8, #4
513+
; CHECK-NEXT: lsl w8, w0, #4
514+
; CHECK-NEXT: and w0, w8, #0x7f00
519515
; CHECK-NEXT: ret
520516
%t0 = and i16 %a0, 2032
521517
%t1 = shl i16 %t0, 4
@@ -524,8 +520,8 @@ define i16 @test_i16_2032_mask_shl_4(i16 %a0) {
524520
define i16 @test_i16_2032_mask_shl_5(i16 %a0) {
525521
; CHECK-LABEL: test_i16_2032_mask_shl_5:
526522
; CHECK: // %bb.0:
527-
; CHECK-NEXT: and w8, w0, #0x7f0
528-
; CHECK-NEXT: lsl w0, w8, #5
523+
; CHECK-NEXT: lsl w8, w0, #5
524+
; CHECK-NEXT: and w0, w8, #0xfe00
529525
; CHECK-NEXT: ret
530526
%t0 = and i16 %a0, 2032
531527
%t1 = shl i16 %t0, 5
@@ -534,8 +530,8 @@ define i16 @test_i16_2032_mask_shl_5(i16 %a0) {
534530
define i16 @test_i16_2032_mask_shl_6(i16 %a0) {
535531
; CHECK-LABEL: test_i16_2032_mask_shl_6:
536532
; CHECK: // %bb.0:
537-
; CHECK-NEXT: and w8, w0, #0x3f0
538-
; CHECK-NEXT: lsl w0, w8, #6
533+
; CHECK-NEXT: lsl w8, w0, #6
534+
; CHECK-NEXT: and w0, w8, #0xfc00
539535
; CHECK-NEXT: ret
540536
%t0 = and i16 %a0, 2032
541537
%t1 = shl i16 %t0, 6
@@ -545,8 +541,8 @@ define i16 @test_i16_2032_mask_shl_6(i16 %a0) {
545541
define i16 @test_i16_65024_mask_shl_1(i16 %a0) {
546542
; CHECK-LABEL: test_i16_65024_mask_shl_1:
547543
; CHECK: // %bb.0:
548-
; CHECK-NEXT: and w8, w0, #0x7e00
549-
; CHECK-NEXT: lsl w0, w8, #1
544+
; CHECK-NEXT: lsl w8, w0, #1
545+
; CHECK-NEXT: and w0, w8, #0xfc00
550546
; CHECK-NEXT: ret
551547
%t0 = and i16 %a0, 65024
552548
%t1 = shl i16 %t0, 1
@@ -740,8 +736,7 @@ define i32 @test_i32_4294836224_mask_ashr_18(i32 %a0) {
740736
define i32 @test_i32_32767_mask_shl_1(i32 %a0) {
741737
; CHECK-LABEL: test_i32_32767_mask_shl_1:
742738
; CHECK: // %bb.0:
743-
; CHECK-NEXT: and w8, w0, #0x7fff
744-
; CHECK-NEXT: lsl w0, w8, #1
739+
; CHECK-NEXT: ubfiz w0, w0, #1, #15
745740
; CHECK-NEXT: ret
746741
%t0 = and i32 %a0, 32767
747742
%t1 = shl i32 %t0, 1
@@ -750,8 +745,7 @@ define i32 @test_i32_32767_mask_shl_1(i32 %a0) {
750745
define i32 @test_i32_32767_mask_shl_16(i32 %a0) {
751746
; CHECK-LABEL: test_i32_32767_mask_shl_16:
752747
; CHECK: // %bb.0:
753-
; CHECK-NEXT: and w8, w0, #0x7fff
754-
; CHECK-NEXT: lsl w0, w8, #16
748+
; CHECK-NEXT: ubfiz w0, w0, #16, #15
755749
; CHECK-NEXT: ret
756750
%t0 = and i32 %a0, 32767
757751
%t1 = shl i32 %t0, 16
@@ -779,8 +773,8 @@ define i32 @test_i32_32767_mask_shl_18(i32 %a0) {
779773
define i32 @test_i32_8388352_mask_shl_7(i32 %a0) {
780774
; CHECK-LABEL: test_i32_8388352_mask_shl_7:
781775
; CHECK: // %bb.0:
782-
; CHECK-NEXT: and w8, w0, #0x7fff00
783-
; CHECK-NEXT: lsl w0, w8, #7
776+
; CHECK-NEXT: lsl w8, w0, #7
777+
; CHECK-NEXT: and w0, w8, #0x3fff8000
784778
; CHECK-NEXT: ret
785779
%t0 = and i32 %a0, 8388352
786780
%t1 = shl i32 %t0, 7
@@ -789,8 +783,8 @@ define i32 @test_i32_8388352_mask_shl_7(i32 %a0) {
789783
define i32 @test_i32_8388352_mask_shl_8(i32 %a0) {
790784
; CHECK-LABEL: test_i32_8388352_mask_shl_8:
791785
; CHECK: // %bb.0:
792-
; CHECK-NEXT: and w8, w0, #0x7fff00
793-
; CHECK-NEXT: lsl w0, w8, #8
786+
; CHECK-NEXT: lsl w8, w0, #8
787+
; CHECK-NEXT: and w0, w8, #0x7fff0000
794788
; CHECK-NEXT: ret
795789
%t0 = and i32 %a0, 8388352
796790
%t1 = shl i32 %t0, 8
@@ -799,8 +793,8 @@ define i32 @test_i32_8388352_mask_shl_8(i32 %a0) {
799793
define i32 @test_i32_8388352_mask_shl_9(i32 %a0) {
800794
; CHECK-LABEL: test_i32_8388352_mask_shl_9:
801795
; CHECK: // %bb.0:
802-
; CHECK-NEXT: and w8, w0, #0x7fff00
803-
; CHECK-NEXT: lsl w0, w8, #9
796+
; CHECK-NEXT: lsl w8, w0, #9
797+
; CHECK-NEXT: and w0, w8, #0xfffe0000
804798
; CHECK-NEXT: ret
805799
%t0 = and i32 %a0, 8388352
806800
%t1 = shl i32 %t0, 9
@@ -809,8 +803,8 @@ define i32 @test_i32_8388352_mask_shl_9(i32 %a0) {
809803
define i32 @test_i32_8388352_mask_shl_10(i32 %a0) {
810804
; CHECK-LABEL: test_i32_8388352_mask_shl_10:
811805
; CHECK: // %bb.0:
812-
; CHECK-NEXT: and w8, w0, #0x3fff00
813-
; CHECK-NEXT: lsl w0, w8, #10
806+
; CHECK-NEXT: lsl w8, w0, #10
807+
; CHECK-NEXT: and w0, w8, #0xfffc0000
814808
; CHECK-NEXT: ret
815809
%t0 = and i32 %a0, 8388352
816810
%t1 = shl i32 %t0, 10
@@ -820,8 +814,8 @@ define i32 @test_i32_8388352_mask_shl_10(i32 %a0) {
820814
define i32 @test_i32_4294836224_mask_shl_1(i32 %a0) {
821815
; CHECK-LABEL: test_i32_4294836224_mask_shl_1:
822816
; CHECK: // %bb.0:
823-
; CHECK-NEXT: and w8, w0, #0x7ffe0000
824-
; CHECK-NEXT: lsl w0, w8, #1
817+
; CHECK-NEXT: lsl w8, w0, #1
818+
; CHECK-NEXT: and w0, w8, #0xfffc0000
825819
; CHECK-NEXT: ret
826820
%t0 = and i32 %a0, 4294836224
827821
%t1 = shl i32 %t0, 1
@@ -1015,8 +1009,7 @@ define i64 @test_i64_18446744065119617024_mask_ashr_34(i64 %a0) {
10151009
define i64 @test_i64_2147483647_mask_shl_1(i64 %a0) {
10161010
; CHECK-LABEL: test_i64_2147483647_mask_shl_1:
10171011
; CHECK: // %bb.0:
1018-
; CHECK-NEXT: and x8, x0, #0x7fffffff
1019-
; CHECK-NEXT: lsl x0, x8, #1
1012+
; CHECK-NEXT: lsl w0, w0, #1
10201013
; CHECK-NEXT: ret
10211014
%t0 = and i64 %a0, 2147483647
10221015
%t1 = shl i64 %t0, 1
@@ -1054,8 +1047,8 @@ define i64 @test_i64_2147483647_mask_shl_34(i64 %a0) {
10541047
define i64 @test_i64_140737488289792_mask_shl_15(i64 %a0) {
10551048
; CHECK-LABEL: test_i64_140737488289792_mask_shl_15:
10561049
; CHECK: // %bb.0:
1057-
; CHECK-NEXT: and x8, x0, #0x7fffffff0000
1058-
; CHECK-NEXT: lsl x0, x8, #15
1050+
; CHECK-NEXT: lsl x8, x0, #15
1051+
; CHECK-NEXT: and x0, x8, #0x3fffffff80000000
10591052
; CHECK-NEXT: ret
10601053
%t0 = and i64 %a0, 140737488289792
10611054
%t1 = shl i64 %t0, 15
@@ -1064,8 +1057,8 @@ define i64 @test_i64_140737488289792_mask_shl_15(i64 %a0) {
10641057
define i64 @test_i64_140737488289792_mask_shl_16(i64 %a0) {
10651058
; CHECK-LABEL: test_i64_140737488289792_mask_shl_16:
10661059
; CHECK: // %bb.0:
1067-
; CHECK-NEXT: and x8, x0, #0x7fffffff0000
1068-
; CHECK-NEXT: lsl x0, x8, #16
1060+
; CHECK-NEXT: lsl x8, x0, #16
1061+
; CHECK-NEXT: and x0, x8, #0x7fffffff00000000
10691062
; CHECK-NEXT: ret
10701063
%t0 = and i64 %a0, 140737488289792
10711064
%t1 = shl i64 %t0, 16
@@ -1074,8 +1067,8 @@ define i64 @test_i64_140737488289792_mask_shl_16(i64 %a0) {
10741067
define i64 @test_i64_140737488289792_mask_shl_17(i64 %a0) {
10751068
; CHECK-LABEL: test_i64_140737488289792_mask_shl_17:
10761069
; CHECK: // %bb.0:
1077-
; CHECK-NEXT: and x8, x0, #0x7fffffff0000
1078-
; CHECK-NEXT: lsl x0, x8, #17
1070+
; CHECK-NEXT: lsl x8, x0, #17
1071+
; CHECK-NEXT: and x0, x8, #0xfffffffe00000000
10791072
; CHECK-NEXT: ret
10801073
%t0 = and i64 %a0, 140737488289792
10811074
%t1 = shl i64 %t0, 17
@@ -1084,8 +1077,8 @@ define i64 @test_i64_140737488289792_mask_shl_17(i64 %a0) {
10841077
define i64 @test_i64_140737488289792_mask_shl_18(i64 %a0) {
10851078
; CHECK-LABEL: test_i64_140737488289792_mask_shl_18:
10861079
; CHECK: // %bb.0:
1087-
; CHECK-NEXT: and x8, x0, #0x3fffffff0000
1088-
; CHECK-NEXT: lsl x0, x8, #18
1080+
; CHECK-NEXT: lsl x8, x0, #18
1081+
; CHECK-NEXT: and x0, x8, #0xfffffffc00000000
10891082
; CHECK-NEXT: ret
10901083
%t0 = and i64 %a0, 140737488289792
10911084
%t1 = shl i64 %t0, 18
@@ -1095,8 +1088,8 @@ define i64 @test_i64_140737488289792_mask_shl_18(i64 %a0) {
10951088
define i64 @test_i64_18446744065119617024_mask_shl_1(i64 %a0) {
10961089
; CHECK-LABEL: test_i64_18446744065119617024_mask_shl_1:
10971090
; CHECK: // %bb.0:
1098-
; CHECK-NEXT: and x8, x0, #0x7ffffffe00000000
1099-
; CHECK-NEXT: lsl x0, x8, #1
1091+
; CHECK-NEXT: lsl x8, x0, #1
1092+
; CHECK-NEXT: and x0, x8, #0xfffffffc00000000
11001093
; CHECK-NEXT: ret
11011094
%t0 = and i64 %a0, 18446744065119617024
11021095
%t1 = shl i64 %t0, 1

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