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Thorsten Schütt
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upfate tests
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-102
lines changed

2 files changed

+42
-102
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‎llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1230,8 +1230,8 @@ class LegalizeRuleSet {
12301230
assert(MinTy.getElementType() == MaxTy.getElementType() &&
12311231
"Expected element types to agree");
12321232

1233-
assert((!MinTy.isScalableVector() && !MaxTy.isScalableVector())
1234-
&& "Unexpected scalable vectors");
1233+
assert((!MinTy.isScalableVector() && !MaxTy.isScalableVector()) &&
1234+
"Unexpected scalable vectors");
12351235

12361236
const LLT EltTy = MinTy.getElementType();
12371237
return clampMinNumElements(TypeIdx, EltTy, MinTy.getNumElements())

‎llvm/test/CodeGen/AArch64/sve-integer.ll

Lines changed: 40 additions & 100 deletions
Original file line numberDiff line numberDiff line change
@@ -3,266 +3,206 @@
33
; RUN: llc < %s -mtriple aarch64 -mattr=+sve -global-isel -aarch64-enable-gisel-sve=1 | FileCheck %s
44

55
;; add
6-
define void @addnxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, ptr %p) {
6+
define <vscale x 2 x i64> @addnxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
77
; CHECK-LABEL: addnxv2i64:
88
; CHECK: // %bb.0: // %entry
99
; CHECK-NEXT: add z0.d, z0.d, z1.d
10-
; CHECK-NEXT: ptrue p0.d
11-
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
1210
; CHECK-NEXT: ret
1311
entry:
1412
%c = add <vscale x 2 x i64> %a, %b
15-
store <vscale x 2 x i64> %c, ptr %p, align 16
16-
ret void
13+
ret <vscale x 2 x i64> %c
1714
}
1815

19-
define void @addnxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, ptr %p) {
16+
define <vscale x 4 x i32> @addnxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
2017
; CHECK-LABEL: addnxv4i32:
2118
; CHECK: // %bb.0: // %entry
2219
; CHECK-NEXT: add z0.s, z0.s, z1.s
23-
; CHECK-NEXT: ptrue p0.s
24-
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
2520
; CHECK-NEXT: ret
2621
entry:
2722
%c = add <vscale x 4 x i32> %a, %b
28-
store <vscale x 4 x i32> %c, ptr %p, align 16
29-
ret void
23+
ret <vscale x 4 x i32> %c
3024
}
3125

32-
define void @addnxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, ptr %p) {
26+
define <vscale x 8 x i16> @addnxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, ptr %p) {
3327
; CHECK-LABEL: addnxv8i16:
3428
; CHECK: // %bb.0: // %entry
3529
; CHECK-NEXT: add z0.h, z0.h, z1.h
36-
; CHECK-NEXT: ptrue p0.h
37-
; CHECK-NEXT: st1h { z0.h }, p0, [x0]
3830
; CHECK-NEXT: ret
3931
entry:
4032
%c = add <vscale x 8 x i16> %a, %b
41-
store <vscale x 8 x i16> %c, ptr %p, align 16
42-
ret void
33+
ret <vscale x 8 x i16> %c
4334
}
4435

45-
define void @addnxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, ptr %p) {
36+
define <vscale x 16 x i8> @addnxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
4637
; CHECK-LABEL: addnxv16i8:
4738
; CHECK: // %bb.0: // %entry
4839
; CHECK-NEXT: add z0.b, z0.b, z1.b
49-
; CHECK-NEXT: ptrue p0.b
50-
; CHECK-NEXT: st1b { z0.b }, p0, [x0]
5140
; CHECK-NEXT: ret
5241
entry:
5342
%c = add <vscale x 16 x i8> %a, %b
54-
store <vscale x 16 x i8> %c, ptr %p, align 16
55-
ret void
43+
ret <vscale x 16 x i8> %c
5644
}
5745

5846
;; sub
59-
define void @subnxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, ptr %p) {
47+
define <vscale x 2 x i64> @subnxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
6048
; CHECK-LABEL: subnxv2i64:
6149
; CHECK: // %bb.0: // %entry
6250
; CHECK-NEXT: sub z0.d, z0.d, z1.d
63-
; CHECK-NEXT: ptrue p0.d
64-
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
6551
; CHECK-NEXT: ret
6652
entry:
6753
%c = sub <vscale x 2 x i64> %a, %b
68-
store <vscale x 2 x i64> %c, ptr %p, align 16
69-
ret void
54+
ret <vscale x 2 x i64> %c
7055
}
7156

72-
define void @subnxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, ptr %p) {
57+
define <vscale x 4 x i32> @subnxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
7358
; CHECK-LABEL: subnxv4i32:
7459
; CHECK: // %bb.0: // %entry
7560
; CHECK-NEXT: sub z0.s, z0.s, z1.s
76-
; CHECK-NEXT: ptrue p0.s
77-
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
7861
; CHECK-NEXT: ret
7962
entry:
8063
%c = sub <vscale x 4 x i32> %a, %b
81-
store <vscale x 4 x i32> %c, ptr %p, align 16
82-
ret void
64+
ret <vscale x 4 x i32> %c
8365
}
8466

85-
define void @subnxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, ptr %p) {
67+
define <vscale x 8 x i16> @subnxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, ptr %p) {
8668
; CHECK-LABEL: subnxv8i16:
8769
; CHECK: // %bb.0: // %entry
8870
; CHECK-NEXT: sub z0.h, z0.h, z1.h
89-
; CHECK-NEXT: ptrue p0.h
90-
; CHECK-NEXT: st1h { z0.h }, p0, [x0]
9171
; CHECK-NEXT: ret
9272
entry:
9373
%c = sub <vscale x 8 x i16> %a, %b
94-
store <vscale x 8 x i16> %c, ptr %p, align 16
95-
ret void
74+
ret <vscale x 8 x i16> %c
9675
}
9776

98-
define void @subnxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, ptr %p) {
77+
define <vscale x 16 x i8> @subnxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
9978
; CHECK-LABEL: subnxv16i8:
10079
; CHECK: // %bb.0: // %entry
10180
; CHECK-NEXT: sub z0.b, z0.b, z1.b
102-
; CHECK-NEXT: ptrue p0.b
103-
; CHECK-NEXT: st1b { z0.b }, p0, [x0]
10481
; CHECK-NEXT: ret
10582
entry:
10683
%c = sub <vscale x 16 x i8> %a, %b
107-
store <vscale x 16 x i8> %c, ptr %p, align 16
108-
ret void
84+
ret <vscale x 16 x i8> %c
10985
}
11086

11187
;; and
112-
define void @andnxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, ptr %p) {
88+
define <vscale x 2 x i64> @andnxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
11389
; CHECK-LABEL: andnxv2i64:
11490
; CHECK: // %bb.0: // %entry
11591
; CHECK-NEXT: and z0.d, z0.d, z1.d
116-
; CHECK-NEXT: ptrue p0.d
117-
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
11892
; CHECK-NEXT: ret
11993
entry:
12094
%c = and <vscale x 2 x i64> %a, %b
121-
store <vscale x 2 x i64> %c, ptr %p, align 16
122-
ret void
95+
ret <vscale x 2 x i64> %c
12396
}
12497

125-
define void @andnxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, ptr %p) {
98+
define <vscale x 4 x i32> @andnxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
12699
; CHECK-LABEL: andnxv4i32:
127100
; CHECK: // %bb.0: // %entry
128101
; CHECK-NEXT: and z0.d, z0.d, z1.d
129-
; CHECK-NEXT: ptrue p0.s
130-
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
131102
; CHECK-NEXT: ret
132103
entry:
133104
%c = and <vscale x 4 x i32> %a, %b
134-
store <vscale x 4 x i32> %c, ptr %p, align 16
135-
ret void
105+
ret <vscale x 4 x i32> %c
136106
}
137107

138-
define void @andnxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, ptr %p) {
108+
define <vscale x 8 x i16> @andnxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, ptr %p) {
139109
; CHECK-LABEL: andnxv8i16:
140110
; CHECK: // %bb.0: // %entry
141111
; CHECK-NEXT: and z0.d, z0.d, z1.d
142-
; CHECK-NEXT: ptrue p0.h
143-
; CHECK-NEXT: st1h { z0.h }, p0, [x0]
144112
; CHECK-NEXT: ret
145113
entry:
146114
%c = and <vscale x 8 x i16> %a, %b
147-
store <vscale x 8 x i16> %c, ptr %p, align 16
148-
ret void
115+
ret <vscale x 8 x i16> %c
149116
}
150117

151-
define void @andnxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, ptr %p) {
118+
define <vscale x 16 x i8> @andnxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
152119
; CHECK-LABEL: andnxv16i8:
153120
; CHECK: // %bb.0: // %entry
154121
; CHECK-NEXT: and z0.d, z0.d, z1.d
155-
; CHECK-NEXT: ptrue p0.b
156-
; CHECK-NEXT: st1b { z0.b }, p0, [x0]
157122
; CHECK-NEXT: ret
158123
entry:
159124
%c = and <vscale x 16 x i8> %a, %b
160-
store <vscale x 16 x i8> %c, ptr %p, align 16
161-
ret void
125+
ret <vscale x 16 x i8> %c
162126
}
163127

164128
;; or
165-
define void @ornxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, ptr %p) {
129+
define <vscale x 2 x i64> @ornxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
166130
; CHECK-LABEL: ornxv2i64:
167131
; CHECK: // %bb.0: // %entry
168132
; CHECK-NEXT: orr z0.d, z0.d, z1.d
169-
; CHECK-NEXT: ptrue p0.d
170-
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
171133
; CHECK-NEXT: ret
172134
entry:
173135
%c = or <vscale x 2 x i64> %a, %b
174-
store <vscale x 2 x i64> %c, ptr %p, align 16
175-
ret void
136+
ret <vscale x 2 x i64> %c
176137
}
177138

178-
define void @ornxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, ptr %p) {
139+
define <vscale x 4 x i32> @ornxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
179140
; CHECK-LABEL: ornxv4i32:
180141
; CHECK: // %bb.0: // %entry
181142
; CHECK-NEXT: orr z0.d, z0.d, z1.d
182-
; CHECK-NEXT: ptrue p0.s
183-
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
184143
; CHECK-NEXT: ret
185144
entry:
186145
%c = or <vscale x 4 x i32> %a, %b
187-
store <vscale x 4 x i32> %c, ptr %p, align 16
188-
ret void
146+
ret <vscale x 4 x i32> %c
189147
}
190148

191-
define void @ornxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, ptr %p) {
149+
define <vscale x 8 x i16> @ornxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, ptr %p) {
192150
; CHECK-LABEL: ornxv8i16:
193151
; CHECK: // %bb.0: // %entry
194152
; CHECK-NEXT: orr z0.d, z0.d, z1.d
195-
; CHECK-NEXT: ptrue p0.h
196-
; CHECK-NEXT: st1h { z0.h }, p0, [x0]
197153
; CHECK-NEXT: ret
198154
entry:
199155
%c = or <vscale x 8 x i16> %a, %b
200-
store <vscale x 8 x i16> %c, ptr %p, align 16
201-
ret void
156+
ret <vscale x 8 x i16> %c
202157
}
203158

204-
define void @ornxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, ptr %p) {
159+
define <vscale x 16 x i8> @ornxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
205160
; CHECK-LABEL: ornxv16i8:
206161
; CHECK: // %bb.0: // %entry
207162
; CHECK-NEXT: orr z0.d, z0.d, z1.d
208-
; CHECK-NEXT: ptrue p0.b
209-
; CHECK-NEXT: st1b { z0.b }, p0, [x0]
210163
; CHECK-NEXT: ret
211164
entry:
212165
%c = or <vscale x 16 x i8> %a, %b
213-
store <vscale x 16 x i8> %c, ptr %p, align 16
214-
ret void
166+
ret <vscale x 16 x i8> %c
215167
}
216168

217169
;; xor
218-
define void @xornxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, ptr %p) {
170+
define <vscale x 2 x i64> @xornxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
219171
; CHECK-LABEL: xornxv2i64:
220172
; CHECK: // %bb.0: // %entry
221173
; CHECK-NEXT: eor z0.d, z0.d, z1.d
222-
; CHECK-NEXT: ptrue p0.d
223-
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
224174
; CHECK-NEXT: ret
225175
entry:
226176
%c = xor <vscale x 2 x i64> %a, %b
227-
store <vscale x 2 x i64> %c, ptr %p, align 16
228-
ret void
177+
ret <vscale x 2 x i64> %c
229178
}
230179

231-
define void @xornxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, ptr %p) {
180+
define <vscale x 4 x i32> @xornxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
232181
; CHECK-LABEL: xornxv4i32:
233182
; CHECK: // %bb.0: // %entry
234183
; CHECK-NEXT: eor z0.d, z0.d, z1.d
235-
; CHECK-NEXT: ptrue p0.s
236-
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
237184
; CHECK-NEXT: ret
238185
entry:
239186
%c = xor <vscale x 4 x i32> %a, %b
240-
store <vscale x 4 x i32> %c, ptr %p, align 16
241-
ret void
187+
ret <vscale x 4 x i32> %c
242188
}
243189

244-
define void @xornxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, ptr %p) {
190+
define <vscale x 8 x i16> @xornxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, ptr %p) {
245191
; CHECK-LABEL: xornxv8i16:
246192
; CHECK: // %bb.0: // %entry
247193
; CHECK-NEXT: eor z0.d, z0.d, z1.d
248-
; CHECK-NEXT: ptrue p0.h
249-
; CHECK-NEXT: st1h { z0.h }, p0, [x0]
250194
; CHECK-NEXT: ret
251195
entry:
252196
%c = xor <vscale x 8 x i16> %a, %b
253-
store <vscale x 8 x i16> %c, ptr %p, align 16
254-
ret void
197+
ret <vscale x 8 x i16> %c
255198
}
256199

257-
define void @xornxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, ptr %p) {
200+
define <vscale x 16 x i8> @xornxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
258201
; CHECK-LABEL: xornxv16i8:
259202
; CHECK: // %bb.0: // %entry
260203
; CHECK-NEXT: eor z0.d, z0.d, z1.d
261-
; CHECK-NEXT: ptrue p0.b
262-
; CHECK-NEXT: st1b { z0.b }, p0, [x0]
263204
; CHECK-NEXT: ret
264205
entry:
265206
%c = xor <vscale x 16 x i8> %a, %b
266-
store <vscale x 16 x i8> %c, ptr %p, align 16
267-
ret void
207+
ret <vscale x 16 x i8> %c
268208
}

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