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[RISCV] Support vwsll in combineBinOp_VLToVWBinOp_VL
If the subtarget has +zvbb then we can attempt folding shl and shl_vl to vwsll nodes. There are few test cases where we still don't pick up the vwsll: - For fixed vector vwsll.vi on RV32, see the FIXME for VMV_V_X_VL in fillUpExtensionSupport for support implicit sign extension - For scalable vector vwsll.vi we need to support ISD::SPLAT_VECTOR, see #87249
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3 files changed

+89
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‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 37 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -13543,6 +13543,7 @@ enum ExtKind : uint8_t { ZExt = 1 << 0, SExt = 1 << 1, FPExt = 1 << 2 };
1354313543
/// add | add_vl | or disjoint -> vwadd(u) | vwadd(u)_w
1354413544
/// sub | sub_vl -> vwsub(u) | vwsub(u)_w
1354513545
/// mul | mul_vl -> vwmul(u) | vwmul_su
13546+
/// shl | shl_vl -> vwsll
1354613547
/// fadd -> vfwadd | vfwadd_w
1354713548
/// fsub -> vfwsub | vfwsub_w
1354813549
/// fmul -> vfwmul
@@ -13721,6 +13722,9 @@ struct NodeExtensionHelper {
1372113722
case ISD::MUL:
1372213723
case RISCVISD::MUL_VL:
1372313724
return RISCVISD::VWMULU_VL;
13725+
case ISD::SHL:
13726+
case RISCVISD::SHL_VL:
13727+
return RISCVISD::VWSLL_VL;
1372413728
default:
1372513729
llvm_unreachable("Unexpected opcode");
1372613730
}
@@ -13871,7 +13875,8 @@ struct NodeExtensionHelper {
1387113875
}
1387213876

1387313877
/// Check if \p Root supports any extension folding combines.
13874-
static bool isSupportedRoot(const SDNode *Root) {
13878+
static bool isSupportedRoot(const SDNode *Root,
13879+
const RISCVSubtarget &Subtarget) {
1387513880
switch (Root->getOpcode()) {
1387613881
case ISD::ADD:
1387713882
case ISD::SUB:
@@ -13897,6 +13902,11 @@ struct NodeExtensionHelper {
1389713902
case RISCVISD::VFWADD_W_VL:
1389813903
case RISCVISD::VFWSUB_W_VL:
1389913904
return true;
13905+
case ISD::SHL:
13906+
return Root->getValueType(0).isScalableVector() &&
13907+
Subtarget.hasStdExtZvbb();
13908+
case RISCVISD::SHL_VL:
13909+
return Subtarget.hasStdExtZvbb();
1390013910
default:
1390113911
return false;
1390213912
}
@@ -13905,8 +13915,9 @@ struct NodeExtensionHelper {
1390513915
/// Build a NodeExtensionHelper for \p Root.getOperand(\p OperandIdx).
1390613916
NodeExtensionHelper(SDNode *Root, unsigned OperandIdx, SelectionDAG &DAG,
1390713917
const RISCVSubtarget &Subtarget) {
13908-
assert(isSupportedRoot(Root) && "Trying to build an helper with an "
13909-
"unsupported root");
13918+
assert(isSupportedRoot(Root, Subtarget) &&
13919+
"Trying to build an helper with an "
13920+
"unsupported root");
1391013921
assert(OperandIdx < 2 && "Requesting something else than LHS or RHS");
1391113922
assert(DAG.getTargetLoweringInfo().isTypeLegal(Root->getValueType(0)));
1391213923
OrigOperand = Root->getOperand(OperandIdx);
@@ -13958,12 +13969,13 @@ struct NodeExtensionHelper {
1395813969
static std::pair<SDValue, SDValue>
1395913970
getMaskAndVL(const SDNode *Root, SelectionDAG &DAG,
1396013971
const RISCVSubtarget &Subtarget) {
13961-
assert(isSupportedRoot(Root) && "Unexpected root");
13972+
assert(isSupportedRoot(Root, Subtarget) && "Unexpected root");
1396213973
switch (Root->getOpcode()) {
1396313974
case ISD::ADD:
1396413975
case ISD::SUB:
1396513976
case ISD::MUL:
13966-
case ISD::OR: {
13977+
case ISD::OR:
13978+
case ISD::SHL: {
1396713979
SDLoc DL(Root);
1396813980
MVT VT = Root->getSimpleValueType(0);
1396913981
return getDefaultScalableVLOps(VT, DL, DAG, Subtarget);
@@ -14001,6 +14013,8 @@ struct NodeExtensionHelper {
1400114013
case RISCVISD::VWSUBU_W_VL:
1400214014
case RISCVISD::FSUB_VL:
1400314015
case RISCVISD::VFWSUB_W_VL:
14016+
case ISD::SHL:
14017+
case RISCVISD::SHL_VL:
1400414018
return false;
1400514019
default:
1400614020
llvm_unreachable("Unexpected opcode");
@@ -14054,6 +14068,7 @@ struct CombineResult {
1405414068
case ISD::SUB:
1405514069
case ISD::MUL:
1405614070
case ISD::OR:
14071+
case ISD::SHL:
1405714072
Merge = DAG.getUNDEF(Root->getValueType(0));
1405814073
break;
1405914074
}
@@ -14224,6 +14239,11 @@ NodeExtensionHelper::getSupportedFoldings(const SDNode *Root) {
1422414239
// mul -> vwmulsu
1422514240
Strategies.push_back(canFoldToVW_SU);
1422614241
break;
14242+
case ISD::SHL:
14243+
case RISCVISD::SHL_VL:
14244+
// shl -> vwsll
14245+
Strategies.push_back(canFoldToVWWithZEXT);
14246+
break;
1422714247
case RISCVISD::VWADD_W_VL:
1422814248
case RISCVISD::VWSUB_W_VL:
1422914249
// vwadd_w|vwsub_w -> vwadd|vwsub
@@ -14251,6 +14271,7 @@ NodeExtensionHelper::getSupportedFoldings(const SDNode *Root) {
1425114271
/// add | add_vl | or disjoint -> vwadd(u) | vwadd(u)_w
1425214272
/// sub | sub_vl -> vwsub(u) | vwsub(u)_w
1425314273
/// mul | mul_vl -> vwmul(u) | vwmul_su
14274+
/// shl | shl_vl -> vwsll
1425414275
/// fadd_vl -> vfwadd | vfwadd_w
1425514276
/// fsub_vl -> vfwsub | vfwsub_w
1425614277
/// fmul_vl -> vfwmul
@@ -14265,7 +14286,7 @@ static SDValue combineBinOp_VLToVWBinOp_VL(SDNode *N,
1426514286
if (DCI.isBeforeLegalize())
1426614287
return SDValue();
1426714288

14268-
if (!NodeExtensionHelper::isSupportedRoot(N))
14289+
if (!NodeExtensionHelper::isSupportedRoot(N, Subtarget))
1426914290
return SDValue();
1427014291

1427114292
SmallVector<SDNode *> Worklist;
@@ -14276,7 +14297,7 @@ static SDValue combineBinOp_VLToVWBinOp_VL(SDNode *N,
1427614297

1427714298
while (!Worklist.empty()) {
1427814299
SDNode *Root = Worklist.pop_back_val();
14279-
if (!NodeExtensionHelper::isSupportedRoot(Root))
14300+
if (!NodeExtensionHelper::isSupportedRoot(Root, Subtarget))
1428014301
return SDValue();
1428114302

1428214303
NodeExtensionHelper LHS(N, 0, DAG, Subtarget);
@@ -16371,9 +16392,12 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
1637116392
VPSN->getMemOperand(), IndexType);
1637216393
break;
1637316394
}
16395+
case RISCVISD::SHL_VL:
16396+
if (SDValue V = combineBinOp_VLToVWBinOp_VL(N, DCI, Subtarget))
16397+
return V;
16398+
[[fallthrough]];
1637416399
case RISCVISD::SRA_VL:
16375-
case RISCVISD::SRL_VL:
16376-
case RISCVISD::SHL_VL: {
16400+
case RISCVISD::SRL_VL: {
1637716401
SDValue ShAmt = N->getOperand(1);
1637816402
if (ShAmt.getOpcode() == RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL) {
1637916403
// We don't need the upper 32 bits of a 64-bit element for a shift amount.
@@ -16393,6 +16417,10 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
1639316417
[[fallthrough]];
1639416418
case ISD::SRL:
1639516419
case ISD::SHL: {
16420+
if (N->getOpcode() == ISD::SHL) {
16421+
if (SDValue V = combineBinOp_VLToVWBinOp_VL(N, DCI, Subtarget))
16422+
return V;
16423+
}
1639616424
SDValue ShAmt = N->getOperand(1);
1639716425
if (ShAmt.getOpcode() == RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL) {
1639816426
// We don't need the upper 32 bits of a 64-bit element for a shift amount.

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll

Lines changed: 40 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -111,8 +111,7 @@ define <4 x i64> @vwsll_vx_i32_v4i64_zext(<4 x i32> %a, i32 %b) {
111111
; CHECK-ZVBB-LABEL: vwsll_vx_i32_v4i64_zext:
112112
; CHECK-ZVBB: # %bb.0:
113113
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
114-
; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
115-
; CHECK-ZVBB-NEXT: vwsll.vv v10, v8, v9
114+
; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0
116115
; CHECK-ZVBB-NEXT: vmv2r.v v8, v10
117116
; CHECK-ZVBB-NEXT: ret
118117
%head = insertelement <4 x i32> poison, i32 %b, i32 0
@@ -371,8 +370,7 @@ define <8 x i32> @vwsll_vx_i16_v8i32_zext(<8 x i16> %a, i16 %b) {
371370
; CHECK-ZVBB-LABEL: vwsll_vx_i16_v8i32_zext:
372371
; CHECK-ZVBB: # %bb.0:
373372
; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
374-
; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
375-
; CHECK-ZVBB-NEXT: vwsll.vv v10, v8, v9
373+
; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0
376374
; CHECK-ZVBB-NEXT: vmv2r.v v8, v10
377375
; CHECK-ZVBB-NEXT: ret
378376
%head = insertelement <8 x i16> poison, i16 %b, i32 0
@@ -642,8 +640,7 @@ define <16 x i16> @vwsll_vx_i8_v16i16_zext(<16 x i8> %a, i8 %b) {
642640
; CHECK-ZVBB-LABEL: vwsll_vx_i8_v16i16_zext:
643641
; CHECK-ZVBB: # %bb.0:
644642
; CHECK-ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma
645-
; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
646-
; CHECK-ZVBB-NEXT: vwsll.vv v10, v8, v9
643+
; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0
647644
; CHECK-ZVBB-NEXT: vmv2r.v v8, v10
648645
; CHECK-ZVBB-NEXT: ret
649646
%head = insertelement <16 x i8> poison, i8 %b, i32 0
@@ -710,10 +707,10 @@ define <4 x i64> @vwsll_vv_v4i64_v4i8_zext(<4 x i8> %a, <4 x i8> %b) {
710707
;
711708
; CHECK-ZVBB-LABEL: vwsll_vv_v4i64_v4i8_zext:
712709
; CHECK-ZVBB: # %bb.0:
713-
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
714-
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
715-
; CHECK-ZVBB-NEXT: vzext.vf8 v12, v9
716-
; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
710+
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
711+
; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8
712+
; CHECK-ZVBB-NEXT: vzext.vf4 v11, v9
713+
; CHECK-ZVBB-NEXT: vwsll.vv v8, v10, v11
717714
; CHECK-ZVBB-NEXT: ret
718715
%x = zext <4 x i8> %a to <4 x i64>
719716
%y = zext <4 x i8> %b to <4 x i64>
@@ -784,11 +781,8 @@ define <4 x i64> @vwsll_vx_i32_v4i64_v4i8_zext(<4 x i8> %a, i32 %b) {
784781
; CHECK-ZVBB-LABEL: vwsll_vx_i32_v4i64_v4i8_zext:
785782
; CHECK-ZVBB: # %bb.0:
786783
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
787-
; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
788-
; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
789-
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
790-
; CHECK-ZVBB-NEXT: vzext.vf2 v12, v9
791-
; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
784+
; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8
785+
; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
792786
; CHECK-ZVBB-NEXT: ret
793787
%head = insertelement <4 x i32> poison, i32 %b, i32 0
794788
%splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer
@@ -839,12 +833,9 @@ define <4 x i64> @vwsll_vx_i16_v4i64_v4i8_zext(<4 x i8> %a, i16 %b) {
839833
;
840834
; CHECK-ZVBB-LABEL: vwsll_vx_i16_v4i64_v4i8_zext:
841835
; CHECK-ZVBB: # %bb.0:
842-
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
843-
; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
844-
; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
845-
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
846-
; CHECK-ZVBB-NEXT: vzext.vf4 v12, v9
847-
; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
836+
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
837+
; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8
838+
; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
848839
; CHECK-ZVBB-NEXT: ret
849840
%head = insertelement <4 x i16> poison, i16 %b, i32 0
850841
%splat = shufflevector <4 x i16> %head, <4 x i16> poison, <4 x i32> zeroinitializer
@@ -895,12 +886,9 @@ define <4 x i64> @vwsll_vx_i8_v4i64_v4i8_zext(<4 x i8> %a, i8 %b) {
895886
;
896887
; CHECK-ZVBB-LABEL: vwsll_vx_i8_v4i64_v4i8_zext:
897888
; CHECK-ZVBB: # %bb.0:
898-
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
899-
; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
900-
; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
901-
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
902-
; CHECK-ZVBB-NEXT: vzext.vf8 v12, v9
903-
; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
889+
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
890+
; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8
891+
; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
904892
; CHECK-ZVBB-NEXT: ret
905893
%head = insertelement <4 x i8> poison, i8 %b, i32 0
906894
%splat = shufflevector <4 x i8> %head, <4 x i8> poison, <4 x i32> zeroinitializer
@@ -918,12 +906,31 @@ define <4 x i64> @vwsll_vi_v4i64_v4i8(<4 x i8> %a) {
918906
; CHECK-NEXT: vsll.vi v8, v10, 2
919907
; CHECK-NEXT: ret
920908
;
921-
; CHECK-ZVBB-LABEL: vwsll_vi_v4i64_v4i8:
922-
; CHECK-ZVBB: # %bb.0:
923-
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
924-
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
925-
; CHECK-ZVBB-NEXT: vsll.vi v8, v10, 2
926-
; CHECK-ZVBB-NEXT: ret
909+
; CHECK-ZVBB-RV32-LABEL: vwsll_vi_v4i64_v4i8:
910+
; CHECK-ZVBB-RV32: # %bb.0:
911+
; CHECK-ZVBB-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
912+
; CHECK-ZVBB-RV32-NEXT: vzext.vf8 v10, v8
913+
; CHECK-ZVBB-RV32-NEXT: vsll.vi v8, v10, 2
914+
; CHECK-ZVBB-RV32-NEXT: ret
915+
;
916+
; CHECK-ZVBB-RV64-LABEL: vwsll_vi_v4i64_v4i8:
917+
; CHECK-ZVBB-RV64: # %bb.0:
918+
; CHECK-ZVBB-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
919+
; CHECK-ZVBB-RV64-NEXT: vzext.vf4 v10, v8
920+
; CHECK-ZVBB-RV64-NEXT: vwsll.vi v8, v10, 2
921+
; CHECK-ZVBB-RV64-NEXT: ret
922+
; CHECK-ZVBB32-LABEL: vwsll_vi_v4i64_v4i8:
923+
; CHECK-ZVBB32: # %bb.0:
924+
; CHECK-ZVBB32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
925+
; CHECK-ZVBB32-NEXT: vzext.vf8 v10, v8
926+
; CHECK-ZVBB32-NEXT: vsll.vi v8, v10, 2
927+
; CHECK-ZVBB32-NEXT: ret
928+
; CHECK-ZVBB64-LABEL: vwsll_vi_v4i64_v4i8:
929+
; CHECK-ZVBB64: # %bb.0:
930+
; CHECK-ZVBB64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
931+
; CHECK-ZVBB64-NEXT: vzext.vf4 v10, v8
932+
; CHECK-ZVBB64-NEXT: vwsll.vi v8, v10, 2
933+
; CHECK-ZVBB64-NEXT: ret
927934
%x = zext <4 x i8> %a to <4 x i64>
928935
%z = shl <4 x i64> %x, splat (i64 2)
929936
ret <4 x i64> %z

‎llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll

Lines changed: 12 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -665,10 +665,10 @@ define <vscale x 2 x i64> @vwsll_vv_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, <v
665665
;
666666
; CHECK-ZVBB-LABEL: vwsll_vv_nxv2i64_nxv2i8_zext:
667667
; CHECK-ZVBB: # %bb.0:
668-
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
669-
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
670-
; CHECK-ZVBB-NEXT: vzext.vf8 v12, v9
671-
; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
668+
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
669+
; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8
670+
; CHECK-ZVBB-NEXT: vzext.vf4 v11, v9
671+
; CHECK-ZVBB-NEXT: vwsll.vv v8, v10, v11
672672
; CHECK-ZVBB-NEXT: ret
673673
%x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
674674
%y = zext <vscale x 2 x i8> %b to <vscale x 2 x i64>
@@ -739,11 +739,8 @@ define <vscale x 2 x i64> @vwsll_vx_i32_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a
739739
; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_zext:
740740
; CHECK-ZVBB: # %bb.0:
741741
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
742-
; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
743-
; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
744-
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
745-
; CHECK-ZVBB-NEXT: vzext.vf2 v12, v9
746-
; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
742+
; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8
743+
; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
747744
; CHECK-ZVBB-NEXT: ret
748745
%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
749746
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
@@ -794,12 +791,9 @@ define <vscale x 2 x i64> @vwsll_vx_i16_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a
794791
;
795792
; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_zext:
796793
; CHECK-ZVBB: # %bb.0:
797-
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
798-
; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
799-
; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
800-
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
801-
; CHECK-ZVBB-NEXT: vzext.vf4 v12, v9
802-
; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
794+
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
795+
; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8
796+
; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
803797
; CHECK-ZVBB-NEXT: ret
804798
%head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
805799
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
@@ -850,12 +844,9 @@ define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a,
850844
;
851845
; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_zext:
852846
; CHECK-ZVBB: # %bb.0:
853-
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
854-
; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
855-
; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
856-
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
857-
; CHECK-ZVBB-NEXT: vzext.vf8 v12, v9
858-
; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
847+
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
848+
; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8
849+
; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
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; CHECK-ZVBB-NEXT: ret
860851
%head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
861852
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer

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