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[RISCV] Add test for #93578. NFC
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llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll

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@@ -934,3 +934,22 @@ define <vscale x 8 x i32> @vsra_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale
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%vc = ashr <vscale x 8 x i32> %va, %vs
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ret <vscale x 8 x i32> %vc
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}
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; Negative test. We shouldn't look through the vp.trunc as it isn't vlmax like
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; the rest of the code.
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define <vscale x 1 x i8> @vsra_vv_nxv1i8_sext_zext_mixed_trunc(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> %m, i32 %evl) {
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; CHECK-LABEL: vsra_vv_nxv1i8_sext_zext_mixed_trunc:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a0, 7
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; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
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; CHECK-NEXT: vmin.vx v9, v8, a0
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; CHECK-NEXT: vsra.vv v8, v8, v9
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; CHECK-NEXT: ret
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%sexted_va = sext <vscale x 1 x i8> %va to <vscale x 1 x i32>
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%zexted_vb = zext <vscale x 1 x i8> %va to <vscale x 1 x i32>
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%expand = ashr <vscale x 1 x i32> %sexted_va, %zexted_vb
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%vc = trunc <vscale x 1 x i32> %expand to <vscale x 1 x i16>
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%vd = call <vscale x 1 x i8> @llvm.vp.trunc.nxv1i8.nxvi16(<vscale x 1 x i16> %vc, <vscale x 1 x i1> %m, i32 %evl)
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ret <vscale x 1 x i8> %vd
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}
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declare <vscale x 1 x i8> @llvm.vp.trunc.nxv1i8.nxvi16(<vscale x 1 x i16>, <vscale x 1 x i1>, i32)

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