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[CodeGen] Move EnableSinkAndFold to TargetOptions
1 parent ada4056 commit 51b20bb

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5 files changed

+14
-13
lines changed

5 files changed

+14
-13
lines changed

llvm/include/llvm/CodeGen/TargetPassConfig.h

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -131,11 +131,6 @@ class TargetPassConfig : public ImmutablePass {
131131
/// Default setting for -enable-tail-merge on this target.
132132
bool EnableTailMerge = true;
133133

134-
/// Enable sinking of instructions in MachineSink where a computation can be
135-
/// folded into the addressing mode of a memory load/store instruction or
136-
/// replace a copy.
137-
bool EnableSinkAndFold = false;
138-
139134
/// Require processing of functions such that callees are generated before
140135
/// callers.
141136
bool RequireCodeGenSCCOrder = false;
@@ -198,9 +193,6 @@ class TargetPassConfig : public ImmutablePass {
198193
bool getEnableTailMerge() const { return EnableTailMerge; }
199194
void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
200195

201-
bool getEnableSinkAndFold() const { return EnableSinkAndFold; }
202-
void setEnableSinkAndFold(bool Enable) { setOpt(EnableSinkAndFold, Enable); }
203-
204196
bool requiresCodeGenSCCOrder() const { return RequireCodeGenSCCOrder; }
205197
void setRequiresCodeGenSCCOrder(bool Enable = true) {
206198
setOpt(RequireCodeGenSCCOrder, Enable);

llvm/include/llvm/Target/TargetOptions.h

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -137,7 +137,8 @@ namespace llvm {
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ApproxFuncFPMath(false), EnableAIXExtendedAltivecABI(false),
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HonorSignDependentRoundingFPMathOption(false), NoZerosInBSS(false),
139139
GuaranteedTailCallOpt(false), StackSymbolOrdering(true),
140-
EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false),
140+
EnableSinkAndFold(false), EnableFastISel(false),
141+
EnableGlobalISel(false), UseInitArray(false),
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DisableIntegratedAS(false), FunctionSections(false),
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DataSections(false), IgnoreXCOFFVisibility(false),
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XCOFFTracebackTable(true), UniqueSectionNames(true),
@@ -239,6 +240,11 @@ namespace llvm {
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/// they were generated. Default is true.
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unsigned StackSymbolOrdering : 1;
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243+
/// EnableSinkAndFold - Enable sinking of instructions in MachineSink where
244+
/// a computation can be folded into the addressing mode of a memory
245+
/// load/store instruction or replace a copy.
246+
unsigned EnableSinkAndFold : 1;
247+
242248
/// EnableFastISel - This flag enables fast-path instruction selection
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/// which trades away generated code quality in favor of reducing
244250
/// compile time.

llvm/lib/CodeGen/MachineSink.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -54,6 +54,7 @@
5454
#include "llvm/Support/CommandLine.h"
5555
#include "llvm/Support/Debug.h"
5656
#include "llvm/Support/raw_ostream.h"
57+
#include "llvm/Target/TargetMachine.h"
5758
#include <algorithm>
5859
#include <cassert>
5960
#include <cstdint>
@@ -729,7 +730,9 @@ bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
729730
AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
730731
RegClassInfo.runOnMachineFunction(MF);
731732
TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>();
732-
EnableSinkAndFold = PassConfig->getEnableSinkAndFold();
733+
auto &TM = PassConfig->getTM<TargetMachine>();
734+
EnableSinkAndFold = TM.Options.EnableSinkAndFold;
735+
// EnableSinkAndFold = PassConfig->getEnableSinkAndFold();
733736

734737
bool EverMadeChange = false;
735738

llvm/lib/Target/AArch64/AArch64TargetMachine.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -505,7 +505,7 @@ class AArch64PassConfig : public TargetPassConfig {
505505
: TargetPassConfig(TM, PM) {
506506
if (TM.getOptLevel() != CodeGenOptLevel::None)
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substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
508-
setEnableSinkAndFold(EnableSinkFold);
508+
TM.Options.EnableSinkAndFold = EnableSinkFold;
509509
}
510510

511511
AArch64TargetMachine &getAArch64TargetMachine() const {

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -336,8 +336,8 @@ class RISCVPassConfig : public TargetPassConfig {
336336
RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
337337
: TargetPassConfig(TM, PM) {
338338
if (TM.getOptLevel() != CodeGenOptLevel::None)
339-
substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
340-
setEnableSinkAndFold(EnableSinkFold);
339+
substitutePass(&PostASchedulerID, &PostMachineSchedulerID);
340+
TM.Options.EnableSinkAndFold = EnableSinkFold;
341341
EnableLoopTermFold = true;
342342
}
343343

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