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1 parent 611c96a commit 51c9c82Copy full SHA for 51c9c82
llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
@@ -320,6 +320,19 @@ define i64 @add_shl_moreOneUse_sh3add(i64 %x) {
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ret i64 %add
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}
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+;; Covers a case which previously crashed (pr119527)
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+define i64 @add_shl_sext(i32 %1) {
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+; RV64-LABEL: add_shl_sext:
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+; RV64: # %bb.0:
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+; RV64-NEXT: addi a1, a0, 3
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+; RV64-NEXT: sllw a0, a1, a0
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+; RV64-NEXT: ret
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+ %3 = add i32 %1, 3
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+ %4 = shl i32 %3, %1
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+ %5 = sext i32 %4 to i64
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+ ret i64 %5
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+}
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+
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define i64 @add_shl_moreOneUse_sh4add(i64 %x) {
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; RV64-LABEL: add_shl_moreOneUse_sh4add:
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; RV64: # %bb.0:
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