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djtodorodjtodoro
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Addressing comments
1 parent 7b13261 commit 524e5a7

18 files changed

+287
-245
lines changed

‎clang/include/clang/Driver/Options.td

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4977,10 +4977,6 @@ def msave_restore : Flag<["-"], "msave-restore">, Group<m_riscv_Features_Group>,
49774977
def mno_save_restore : Flag<["-"], "mno-save-restore">, Group<m_riscv_Features_Group>,
49784978
HelpText<"Disable using library calls for save and restore">;
49794979
} // let Flags = [TargetSpecific]
4980-
def mload_store_pairs : Flag<["-"], "mload-store-pairs">, Group<m_riscv_Features_Group>;
4981-
def mno_load_store_pairs : Flag<["-"], "mno-load-store-pairs">, Group<m_riscv_Features_Group>;
4982-
def mccmov : Flag<["-"], "mccmov">, Group<m_riscv_Features_Group>;
4983-
def mno_ccmov : Flag<["-"], "mno-ccmov">, Group<m_riscv_Features_Group>;
49844980
let Flags = [TargetSpecific] in {
49854981
def menable_experimental_extensions : Flag<["-"], "menable-experimental-extensions">, Group<m_Group>,
49864982
HelpText<"Enable use of experimental RISC-V extensions.">;

‎clang/lib/Driver/ToolChains/Clang.cpp

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -2185,21 +2185,6 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args,
21852185
CmdArgs.push_back(A->getValue());
21862186
}
21872187

2188-
if (Arg *A = Args.getLastArg(options::OPT_mload_store_pairs,
2189-
options::OPT_mno_load_store_pairs)) {
2190-
if (A->getOption().matches(options::OPT_mload_store_pairs)) {
2191-
CmdArgs.push_back("-mllvm");
2192-
CmdArgs.push_back("-riscv-load-store-pairs=1");
2193-
}
2194-
}
2195-
2196-
if (Arg *A = Args.getLastArg(options::OPT_mccmov, options::OPT_mno_ccmov)) {
2197-
if (A->getOption().matches(options::OPT_mno_ccmov)) {
2198-
CmdArgs.push_back("-mllvm");
2199-
CmdArgs.push_back("-riscv-ccmov=0");
2200-
}
2201-
}
2202-
22032188
// Handle -mrvv-vector-bits=<bits>
22042189
if (Arg *A = Args.getLastArg(options::OPT_mrvv_vector_bits_EQ)) {
22052190
StringRef Val = A->getValue();

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -667,6 +667,11 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
667667
"SiFive sf.cflush.d.l1 custom opcode table");
668668
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcease, DecoderTableXSfcease32,
669669
"SiFive sf.cease custom opcode table");
670+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorMIPSLoadStorePairs,
671+
DecoderTableXmipslsp32,
672+
"MIPS mips.lsp custom opcode table");
673+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorMIPSCMove, DecoderTableXmipscomve32,
674+
"MIPS mips.ccmov custom opcode table");
670675
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
671676
DecoderTableXCVbitmanip32,
672677
"CORE-V Bit Manipulation custom opcode table");

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 15 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1423,19 +1423,6 @@ def NoConditionalMoveFusion : Predicate<"!Subtarget->hasConditionalMoveFusion()
14231423
def TuneMIPSP8700
14241424
: SubtargetFeature<"mips-p8700", "RISCVProcFamily", "MIPSP8700",
14251425
"MIPS p8700 processor">;
1426-
def FeatureVendorMIPSCMove : SubtargetFeature<"xmipscmove", "HasVendorMIPSCMove",
1427-
"true", "Using CCMov",
1428-
[Feature64Bit]>;
1429-
def HasVendorMIPSCMove
1430-
: Predicate<"Subtarget->useCCMovInsn()">,
1431-
AssemblerPredicate<(all_of FeatureVendorMIPSCMove), "'ccmov' instruction">;
1432-
def FeatureVendorMIPSLoadStorePairs
1433-
: SubtargetFeature<"xmipslsp", "HasMIPSLSP", "true",
1434-
"Optimize for hardware load-store bonding">;
1435-
def HasVendorMIPSLoadStorePairs
1436-
: Predicate<"Subtarget->useLoadStorePairs()">,
1437-
AssemblerPredicate<(all_of FeatureVendorMIPSLoadStorePairs),
1438-
"load and store pair instructions">;
14391426

14401427
def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
14411428
"SiFive 7-Series processors">;
@@ -1461,3 +1448,18 @@ def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
14611448
"AllowTaggedGlobals",
14621449
"true", "Use an instruction sequence for taking the address of a global "
14631450
"that allows a memory tag in the upper address bits">;
1451+
1452+
def FeatureVendorMIPSCMove : SubtargetFeature<"xmipscmove", "HasVendorMIPSCMove",
1453+
"true", "Using CCMov",
1454+
[Feature64Bit]>;
1455+
def HasVendorMIPSCMove
1456+
: Predicate<"Subtarget->useCCMovInsn()">,
1457+
AssemblerPredicate<(all_of FeatureVendorMIPSCMove),
1458+
"'Xmipscmove' ('mips.ccmov' instruction)">;
1459+
def FeatureVendorMIPSLoadStorePairs
1460+
: SubtargetFeature<"xmipslsp", "HasMIPSLSP", "true",
1461+
"Optimize for hardware load-store bonding">;
1462+
def HasVendorMIPSLoadStorePairs
1463+
: Predicate<"Subtarget->useLoadStorePairs()">,
1464+
AssemblerPredicate<(all_of FeatureVendorMIPSLoadStorePairs),
1465+
"'Xmipslsp' (load and store pair instructions)">;

‎llvm/lib/Target/RISCV/RISCVInstrFormats.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -532,7 +532,7 @@ class LDPFormat<dag outs, dag ins, string opcodestr, string argstr>
532532
let Inst{19-15} = rs1;
533533
let Inst{14-12} = 0b100;
534534
let Inst{11-7} = rd1;
535-
let Inst{6-0} = 0b0001011;
535+
let Inst{6-0} = OPC_CUSTOM_0.Value;
536536
}
537537

538538
// Load word pair format.
@@ -549,7 +549,7 @@ class LWPFormat<dag outs, dag ins, string opcodestr, string argstr>
549549
let Inst{19-15} = rs1;
550550
let Inst{14-12} = 0b100;
551551
let Inst{11-7} = rd1;
552-
let Inst{6-0} = 0b0001011;
552+
let Inst{6-0} = OPC_CUSTOM_0.Value;
553553
}
554554

555555
// Store double pair format.

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 0 additions & 140 deletions
Original file line numberDiff line numberDiff line change
@@ -257,146 +257,6 @@ def simm12 : RISCVSImmLeafOp<12> {
257257
}];
258258
}
259259

260-
// A 7-bit unsigned immediate where the least significant two bits are zero.
261-
def uimm7_lsb00 : RISCVOp,
262-
ImmLeaf<XLenVT, [{return isShiftedUInt<5, 2>(Imm);}]> {
263-
let ParserMatchClass = UImmAsmOperand<7, "Lsb00">;
264-
let EncoderMethod = "getImmOpValue";
265-
let DecoderMethod = "decodeUImmOperand<7>";
266-
let OperandType = "OPERAND_UIMM7_LSB00";
267-
let MCOperandPredicate = [{
268-
int64_t Imm;
269-
if (!MCOp.evaluateAsConstantImm(Imm))
270-
return false;
271-
return isShiftedUInt<5, 2>(Imm);
272-
}];
273-
}
274-
275-
// A 7-bit unsigned immediate where the least significant three bits are zero.
276-
def uimm7_lsb000 : RISCVOp,
277-
ImmLeaf<XLenVT, [{return isShiftedUInt<4, 3>(Imm);}]> {
278-
let ParserMatchClass = UImmAsmOperand<7, "Lsb000">;
279-
let EncoderMethod = "getImmOpValue";
280-
let DecoderMethod = "decodeUImmOperand<7>";
281-
let OperandType = "OPERAND_UIMM7_LSB000";
282-
let MCOperandPredicate = [{
283-
int64_t Imm;
284-
if (!MCOp.evaluateAsConstantImm(Imm))
285-
return false;
286-
return isShiftedUInt<4, 3>(Imm);
287-
}];
288-
}
289-
290-
// A 8-bit unsigned immediate where the least significant two bits are zero.
291-
def uimm8_lsb00 : RISCVOp,
292-
ImmLeaf<XLenVT, [{return isShiftedUInt<6, 2>(Imm);}]> {
293-
let ParserMatchClass = UImmAsmOperand<8, "Lsb00">;
294-
let EncoderMethod = "getImmOpValue";
295-
let DecoderMethod = "decodeUImmOperand<8>";
296-
let OperandType = "OPERAND_UIMM8_LSB00";
297-
let MCOperandPredicate = [{
298-
int64_t Imm;
299-
if (!MCOp.evaluateAsConstantImm(Imm))
300-
return false;
301-
return isShiftedUInt<6, 2>(Imm);
302-
}];
303-
}
304-
305-
// A 8-bit unsigned immediate where the least significant three bits are zero.
306-
def uimm8_lsb000 : RISCVOp,
307-
ImmLeaf<XLenVT, [{return isShiftedUInt<5, 3>(Imm);}]> {
308-
let ParserMatchClass = UImmAsmOperand<8, "Lsb000">;
309-
let EncoderMethod = "getImmOpValue";
310-
let DecoderMethod = "decodeUImmOperand<8>";
311-
let OperandType = "OPERAND_UIMM8_LSB000";
312-
let MCOperandPredicate = [{
313-
int64_t Imm;
314-
if (!MCOp.evaluateAsConstantImm(Imm))
315-
return false;
316-
return isShiftedUInt<5, 3>(Imm);
317-
}];
318-
}
319-
320-
// A 9-bit signed immediate where the least significant bit is zero.
321-
def simm9_lsb0 : Operand<OtherVT>,
322-
ImmLeaf<XLenVT, [{return isShiftedInt<8, 1>(Imm);}]> {
323-
let ParserMatchClass = SImmAsmOperand<9, "Lsb0">;
324-
let PrintMethod = "printBranchOperand";
325-
let EncoderMethod = "getImmOpValueAsr1";
326-
let DecoderMethod = "decodeSImmOperandAndLsl1<9>";
327-
let MCOperandPredicate = [{
328-
int64_t Imm;
329-
if (MCOp.evaluateAsConstantImm(Imm))
330-
return isShiftedInt<8, 1>(Imm);
331-
return MCOp.isBareSymbolRef();
332-
}];
333-
let OperandType = "OPERAND_PCREL";
334-
}
335-
336-
// A 9-bit unsigned immediate where the least significant three bits are zero.
337-
def uimm9_lsb000 : RISCVOp,
338-
ImmLeaf<XLenVT, [{return isShiftedUInt<6, 3>(Imm);}]> {
339-
let ParserMatchClass = UImmAsmOperand<9, "Lsb000">;
340-
let EncoderMethod = "getImmOpValue";
341-
let DecoderMethod = "decodeUImmOperand<9>";
342-
let OperandType = "OPERAND_UIMM9_LSB000";
343-
let MCOperandPredicate = [{
344-
int64_t Imm;
345-
if (!MCOp.evaluateAsConstantImm(Imm))
346-
return false;
347-
return isShiftedUInt<6, 3>(Imm);
348-
}];
349-
}
350-
351-
// A 10-bit unsigned immediate where the least significant two bits are zero
352-
// and the immediate can't be zero.
353-
def uimm10_lsb00nonzero : RISCVOp,
354-
ImmLeaf<XLenVT,
355-
[{return isShiftedUInt<8, 2>(Imm) && (Imm != 0);}]> {
356-
let ParserMatchClass = UImmAsmOperand<10, "Lsb00NonZero">;
357-
let EncoderMethod = "getImmOpValue";
358-
let DecoderMethod = "decodeUImmNonZeroOperand<10>";
359-
let OperandType = "OPERAND_UIMM10_LSB00_NONZERO";
360-
let MCOperandPredicate = [{
361-
int64_t Imm;
362-
if (!MCOp.evaluateAsConstantImm(Imm))
363-
return false;
364-
return isShiftedUInt<8, 2>(Imm) && (Imm != 0);
365-
}];
366-
}
367-
368-
// A 10-bit signed immediate where the least significant four bits are zero.
369-
def simm10_lsb0000nonzero : RISCVOp,
370-
ImmLeaf<XLenVT,
371-
[{return (Imm != 0) && isShiftedInt<6, 4>(Imm);}]> {
372-
let ParserMatchClass = SImmAsmOperand<10, "Lsb0000NonZero">;
373-
let EncoderMethod = "getImmOpValue";
374-
let DecoderMethod = "decodeSImmNonZeroOperand<10>";
375-
let OperandType = "OPERAND_SIMM10_LSB0000_NONZERO";
376-
let MCOperandPredicate = [{
377-
int64_t Imm;
378-
if (!MCOp.evaluateAsConstantImm(Imm))
379-
return false;
380-
return isShiftedInt<6, 4>(Imm) && (Imm != 0);
381-
}];
382-
}
383-
384-
// A 12-bit signed immediate where the least significant bit is zero.
385-
def simm12_lsb0 : Operand<XLenVT>,
386-
ImmLeaf<XLenVT, [{return isShiftedInt<11, 1>(Imm);}]> {
387-
let ParserMatchClass = SImmAsmOperand<12, "Lsb0">;
388-
let PrintMethod = "printBranchOperand";
389-
let EncoderMethod = "getImmOpValueAsr1";
390-
let DecoderMethod = "decodeSImmOperandAndLsl1<12>";
391-
let MCOperandPredicate = [{
392-
int64_t Imm;
393-
if (MCOp.evaluateAsConstantImm(Imm))
394-
return isShiftedInt<11, 1>(Imm);
395-
return MCOp.isBareSymbolRef();
396-
}];
397-
let OperandType = "OPERAND_PCREL";
398-
}
399-
400260
// A 12-bit signed immediate which cannot fit in 6-bit signed immediate,
401261
// but even negative value fit in 12-bit.
402262
def simm12_no6 : ImmLeaf<XLenVT, [{

‎llvm/lib/Target/RISCV/RISCVInstrInfoC.td

Lines changed: 140 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -94,6 +94,146 @@ def c_lui_imm : RISCVOp,
9494
}];
9595
}
9696

97+
// A 7-bit unsigned immediate where the least significant two bits are zero.
98+
def uimm7_lsb00 : RISCVOp,
99+
ImmLeaf<XLenVT, [{return isShiftedUInt<5, 2>(Imm);}]> {
100+
let ParserMatchClass = UImmAsmOperand<7, "Lsb00">;
101+
let EncoderMethod = "getImmOpValue";
102+
let DecoderMethod = "decodeUImmOperand<7>";
103+
let OperandType = "OPERAND_UIMM7_LSB00";
104+
let MCOperandPredicate = [{
105+
int64_t Imm;
106+
if (!MCOp.evaluateAsConstantImm(Imm))
107+
return false;
108+
return isShiftedUInt<5, 2>(Imm);
109+
}];
110+
}
111+
112+
// A 7-bit unsigned immediate where the least significant three bits are zero.
113+
def uimm7_lsb000 : RISCVOp,
114+
ImmLeaf<XLenVT, [{return isShiftedUInt<4, 3>(Imm);}]> {
115+
let ParserMatchClass = UImmAsmOperand<7, "Lsb000">;
116+
let EncoderMethod = "getImmOpValue";
117+
let DecoderMethod = "decodeUImmOperand<7>";
118+
let OperandType = "OPERAND_UIMM7_LSB000";
119+
let MCOperandPredicate = [{
120+
int64_t Imm;
121+
if (!MCOp.evaluateAsConstantImm(Imm))
122+
return false;
123+
return isShiftedUInt<4, 3>(Imm);
124+
}];
125+
}
126+
127+
// A 8-bit unsigned immediate where the least significant two bits are zero.
128+
def uimm8_lsb00 : RISCVOp,
129+
ImmLeaf<XLenVT, [{return isShiftedUInt<6, 2>(Imm);}]> {
130+
let ParserMatchClass = UImmAsmOperand<8, "Lsb00">;
131+
let EncoderMethod = "getImmOpValue";
132+
let DecoderMethod = "decodeUImmOperand<8>";
133+
let OperandType = "OPERAND_UIMM8_LSB00";
134+
let MCOperandPredicate = [{
135+
int64_t Imm;
136+
if (!MCOp.evaluateAsConstantImm(Imm))
137+
return false;
138+
return isShiftedUInt<6, 2>(Imm);
139+
}];
140+
}
141+
142+
// A 8-bit unsigned immediate where the least significant three bits are zero.
143+
def uimm8_lsb000 : RISCVOp,
144+
ImmLeaf<XLenVT, [{return isShiftedUInt<5, 3>(Imm);}]> {
145+
let ParserMatchClass = UImmAsmOperand<8, "Lsb000">;
146+
let EncoderMethod = "getImmOpValue";
147+
let DecoderMethod = "decodeUImmOperand<8>";
148+
let OperandType = "OPERAND_UIMM8_LSB000";
149+
let MCOperandPredicate = [{
150+
int64_t Imm;
151+
if (!MCOp.evaluateAsConstantImm(Imm))
152+
return false;
153+
return isShiftedUInt<5, 3>(Imm);
154+
}];
155+
}
156+
157+
// A 9-bit signed immediate where the least significant bit is zero.
158+
def simm9_lsb0 : Operand<OtherVT>,
159+
ImmLeaf<XLenVT, [{return isShiftedInt<8, 1>(Imm);}]> {
160+
let ParserMatchClass = SImmAsmOperand<9, "Lsb0">;
161+
let PrintMethod = "printBranchOperand";
162+
let EncoderMethod = "getImmOpValueAsr1";
163+
let DecoderMethod = "decodeSImmOperandAndLsl1<9>";
164+
let MCOperandPredicate = [{
165+
int64_t Imm;
166+
if (MCOp.evaluateAsConstantImm(Imm))
167+
return isShiftedInt<8, 1>(Imm);
168+
return MCOp.isBareSymbolRef();
169+
}];
170+
let OperandType = "OPERAND_PCREL";
171+
}
172+
173+
// A 9-bit unsigned immediate where the least significant three bits are zero.
174+
def uimm9_lsb000 : RISCVOp,
175+
ImmLeaf<XLenVT, [{return isShiftedUInt<6, 3>(Imm);}]> {
176+
let ParserMatchClass = UImmAsmOperand<9, "Lsb000">;
177+
let EncoderMethod = "getImmOpValue";
178+
let DecoderMethod = "decodeUImmOperand<9>";
179+
let OperandType = "OPERAND_UIMM9_LSB000";
180+
let MCOperandPredicate = [{
181+
int64_t Imm;
182+
if (!MCOp.evaluateAsConstantImm(Imm))
183+
return false;
184+
return isShiftedUInt<6, 3>(Imm);
185+
}];
186+
}
187+
188+
// A 10-bit unsigned immediate where the least significant two bits are zero
189+
// and the immediate can't be zero.
190+
def uimm10_lsb00nonzero : RISCVOp,
191+
ImmLeaf<XLenVT,
192+
[{return isShiftedUInt<8, 2>(Imm) && (Imm != 0);}]> {
193+
let ParserMatchClass = UImmAsmOperand<10, "Lsb00NonZero">;
194+
let EncoderMethod = "getImmOpValue";
195+
let DecoderMethod = "decodeUImmNonZeroOperand<10>";
196+
let OperandType = "OPERAND_UIMM10_LSB00_NONZERO";
197+
let MCOperandPredicate = [{
198+
int64_t Imm;
199+
if (!MCOp.evaluateAsConstantImm(Imm))
200+
return false;
201+
return isShiftedUInt<8, 2>(Imm) && (Imm != 0);
202+
}];
203+
}
204+
205+
// A 10-bit signed immediate where the least significant four bits are zero.
206+
def simm10_lsb0000nonzero : RISCVOp,
207+
ImmLeaf<XLenVT,
208+
[{return (Imm != 0) && isShiftedInt<6, 4>(Imm);}]> {
209+
let ParserMatchClass = SImmAsmOperand<10, "Lsb0000NonZero">;
210+
let EncoderMethod = "getImmOpValue";
211+
let DecoderMethod = "decodeSImmNonZeroOperand<10>";
212+
let OperandType = "OPERAND_SIMM10_LSB0000_NONZERO";
213+
let MCOperandPredicate = [{
214+
int64_t Imm;
215+
if (!MCOp.evaluateAsConstantImm(Imm))
216+
return false;
217+
return isShiftedInt<6, 4>(Imm) && (Imm != 0);
218+
}];
219+
}
220+
221+
// A 12-bit signed immediate where the least significant bit is zero.
222+
def simm12_lsb0 : Operand<XLenVT>,
223+
ImmLeaf<XLenVT, [{return isShiftedInt<11, 1>(Imm);}]> {
224+
let ParserMatchClass = SImmAsmOperand<12, "Lsb0">;
225+
let PrintMethod = "printBranchOperand";
226+
let EncoderMethod = "getImmOpValueAsr1";
227+
let DecoderMethod = "decodeSImmOperandAndLsl1<12>";
228+
let MCOperandPredicate = [{
229+
int64_t Imm;
230+
if (MCOp.evaluateAsConstantImm(Imm))
231+
return isShiftedInt<11, 1>(Imm);
232+
return MCOp.isBareSymbolRef();
233+
}];
234+
let OperandType = "OPERAND_PCREL";
235+
}
236+
97237
def InsnCDirectiveOpcode : AsmOperandClass {
98238
let Name = "InsnCDirectiveOpcode";
99239
let ParserMethod = "parseInsnCDirectiveOpcode";

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