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[RISCV] Support Parsing Nonstandard Relocations (#119909)
This allows nonstandard relocation names to be used in `.reloc` assembly directives (giving the correct relocation number). No translation is done by the assembler into `R_RISCV_CUSTOM<n>` names, and the assembler does not automatically add the relevant `R_RISCV_VENDOR` relocation with the vendor symbol. If we want, we can have a different directive that does this later. The first batch of relocations to be added are from [Qualcomm's RISC-V psABI extensions](https://github.com/quic/riscv-elf-psabi-quic-extensions/releases/tag/v0.1).
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llvm/include/llvm/BinaryFormat/ELF.h

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@@ -689,6 +689,9 @@ enum : unsigned {
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// ELF Relocation types for RISC-V
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enum {
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#include "ELFRelocs/RISCV.def"
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#define ELF_RISCV_NONSTANDARD_RELOC(_vendor, name, value) name = value,
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#include "ELFRelocs/RISCV_nonstandard.def"
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#undef ELF_RISCV_NONSTANDARD_RELOC
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};
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enum {
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@@ -0,0 +1,28 @@
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//===--- RISC-V Nonstandard Relocation List ---------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef ELF_RISCV_NONSTANDARD_RELOC
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#error "ELF_RISCV_NONSTANDARD_RELOC must be defined"
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#endif
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// ELF_RISCV_NONSTANDARD_RELOC(VENDOR, NAME, ID) defines information about
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// nonstandard relocation codes. This can be used when parsing relocations, or
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// when printing them, to provide better information.
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//
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// VENDOR should be the symbol name expected in the associated `R_RISCV_VENDOR`
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// relocation. NAME and ID work like `ELF_RELOC` but the mapping is not expected
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// to be 1:1.
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//
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// The mapping in RISCV.def is 1:1, and should be used when the only information
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// available is the relocation enum value.
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// Qualcomm Nonstandard Relocations
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ELF_RISCV_NONSTANDARD_RELOC(QUALCOMM, R_RISCV_QC_ABS20_U, 192)
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ELF_RISCV_NONSTANDARD_RELOC(QUALCOMM, R_RISCV_QC_E_BRANCH, 193)
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ELF_RISCV_NONSTANDARD_RELOC(QUALCOMM, R_RISCV_QC_E_32, 194)
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ELF_RISCV_NONSTANDARD_RELOC(QUALCOMM, R_RISCV_QC_E_JUMP_PLT, 195)

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

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@@ -38,9 +38,12 @@ std::optional<MCFixupKind> RISCVAsmBackend::getFixupKind(StringRef Name) const {
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if (STI.getTargetTriple().isOSBinFormatELF()) {
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unsigned Type;
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Type = llvm::StringSwitch<unsigned>(Name)
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#define ELF_RELOC(X, Y) .Case(#X, Y)
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#define ELF_RELOC(NAME, ID) .Case(#NAME, ID)
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#include "llvm/BinaryFormat/ELFRelocs/RISCV.def"
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#undef ELF_RELOC
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#define ELF_RISCV_NONSTANDARD_RELOC(_VENDOR, NAME, ID) .Case(#NAME, ID)
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#include "llvm/BinaryFormat/ELFRelocs/RISCV_nonstandard.def"
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#undef ELF_RISCV_NONSTANDARD_RELOC
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.Case("BFD_RELOC_NONE", ELF::R_RISCV_NONE)
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.Case("BFD_RELOC_32", ELF::R_RISCV_32)
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.Case("BFD_RELOC_64", ELF::R_RISCV_64)

llvm/test/MC/RISCV/custom_reloc.s

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@@ -21,16 +21,33 @@
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.reloc ., R_RISCV_VENDOR, VENDOR_NAME
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.reloc ., R_RISCV_CUSTOM192, my_foo + 1
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addi a0, a0, 0
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# CHECK-ASM: [[L1:.L[^:]+]]:
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# CHECK-ASM: [[L1:.L[^:]+]]:
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# CHECK-ASM-NEXT: .reloc [[L1]], R_RISCV_VENDOR, VENDOR_NAME
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# CHECK-ASM-NEXT: [[L2:.L[^:]+]]:
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# CHECK-ASM-NEXT: .reloc [[L2]], R_RISCV_CUSTOM192, my_foo+1
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# CHECK-ASM-NEXT: mv a0, a0
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# CHECK-OBJ: addi a0, a0, 0
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# CHECK-OBJ: addi a0, a0, 0
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# CHECK-OBJ-NEXT: R_RISCV_VENDOR VENDOR_NAME
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# CHECK-OBJ-NEXT: R_RISCV_CUSTOM192 my_foo+0x1
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nop
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# CHECK-ASM: nop
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# CHECK-OBJ: addi zero, zero, 0x0
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.reloc ., R_RISCV_VENDOR, QUALCOMM
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.reloc ., R_RISCV_QC_ABS20_U, my_bar + 2
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addi a1, a1, 0
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# CHECK-ASM: [[L3:.L[^:]+]]:
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# CHECK-ASM-NEXT: .reloc [[L3]], R_RISCV_VENDOR, QUALCOMM
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# CHECK-ASM-NEXT: [[L4:.L[^:]+]]:
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# CHECK-ASM-NEXT: .reloc [[L4]], R_RISCV_QC_ABS20_U, my_bar+2
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# CHECK-ASM-NEXT: mv a1, a1
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# CHECK-OBJ: addi a1, a1, 0
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# CHECK-OBJ-NEXT: R_RISCV_VENDOR QUALCOMM
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# CHECK-OBJ-NEXT: R_RISCV_CUSTOM192 my_bar+0x2
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nop
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# CHECK-ASM: nop
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# CHECK-OBJ: addi zero, zero, 0x0

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