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Pierre-vhPierre-vh
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[AMDGPU] Don't form sext/abs/neg fp8 cvt (#83843)
gfx940 does not allow abs/sext/neg on v_cvt_fp8/bf8 & pk variants. Fixes SWDEV-447468
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‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4726,6 +4726,20 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
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}
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}
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4729+
if (Opcode == AMDGPU::V_CVT_F32_FP8_sdwa ||
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Opcode == AMDGPU::V_CVT_F32_BF8_sdwa ||
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Opcode == AMDGPU::V_CVT_PK_F32_FP8_sdwa ||
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Opcode == AMDGPU::V_CVT_PK_F32_BF8_sdwa) {
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const MachineOperand *Src0ModsMO =
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getNamedOperand(MI, AMDGPU::OpName::src0_modifiers);
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unsigned Mods = Src0ModsMO->getImm();
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if (Mods & SISrcMods::ABS || Mods & SISrcMods::NEG ||
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Mods & SISrcMods::SEXT) {
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ErrInfo = "sext, abs and neg are not allowed on this instruction";
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return false;
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}
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}
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uint16_t BasicOpcode = AMDGPU::getBasicFromSDWAOp(Opcode);
47304744
if (isVOPC(BasicOpcode)) {
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if (!ST.hasSDWASdst() && DstIdx != -1) {

‎llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -338,6 +338,15 @@ MachineInstr *SDWASrcOperand::potentialToConvert(const SIInstrInfo *TII) {
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}
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bool SDWASrcOperand::convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) {
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switch (MI.getOpcode()) {
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case AMDGPU::V_CVT_F32_FP8_sdwa:
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case AMDGPU::V_CVT_F32_BF8_sdwa:
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case AMDGPU::V_CVT_PK_F32_FP8_sdwa:
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case AMDGPU::V_CVT_PK_F32_BF8_sdwa:
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// Does not support input modifiers: noabs, noneg, nosext.
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return false;
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}
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// Find operand in instruction that matches source operand and replace it with
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// target operand. Set corresponding src_sel
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bool IsPreserveSrc = false;

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll

Lines changed: 96 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -534,3 +534,99 @@ define i32 @test_cvt_sr_fp8_f32_byte3(float %x, i32 %r, i32 %old) {
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%ret = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f32(float %x, i32 %r, i32 %old, i32 3)
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ret i32 %ret
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}
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define float @test_sext_cvt_f32_fp8(i16 %a) {
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; GFX940-LABEL: test_sext_cvt_f32_fp8:
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; GFX940: ; %bb.0:
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; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX940-NEXT: v_bfe_i32 v0, v0, 0, 16
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; GFX940-NEXT: v_cvt_f32_fp8_sdwa v0, v0 src0_sel:BYTE_1
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; GFX940-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: test_sext_cvt_f32_fp8:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_bfe_i32 v0, v0, 0, 16
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX12-NEXT: v_cvt_f32_fp8_e64 v0, v0 op_sel:[0,1]
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%a.sext = sext i16 %a to i32
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%ret = tail call float @llvm.amdgcn.cvt.f32.fp8(i32 %a.sext, i32 1)
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ret float %ret
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}
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define float @test_sext_cvt_f32_bf8(i16 %a) {
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; GFX940-LABEL: test_sext_cvt_f32_bf8:
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; GFX940: ; %bb.0:
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; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX940-NEXT: v_bfe_i32 v0, v0, 0, 16
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; GFX940-NEXT: v_cvt_f32_bf8_sdwa v0, v0 src0_sel:BYTE_1
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; GFX940-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: test_sext_cvt_f32_bf8:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_bfe_i32 v0, v0, 0, 16
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX12-NEXT: v_cvt_f32_bf8_e64 v0, v0 op_sel:[0,1]
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%a.sext = sext i16 %a to i32
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%ret = tail call float @llvm.amdgcn.cvt.f32.bf8(i32 %a.sext, i32 1)
583+
ret float %ret
584+
}
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define <2 x float> @test_sext_cvt_pk_f32_bf8_word1(i16 %a) {
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; GFX940-LABEL: test_sext_cvt_pk_f32_bf8_word1:
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; GFX940: ; %bb.0:
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; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX940-NEXT: v_bfe_i32 v0, v0, 0, 16
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; GFX940-NEXT: v_cvt_pk_f32_bf8_sdwa v[0:1], v0 src0_sel:WORD_1
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; GFX940-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: test_sext_cvt_pk_f32_bf8_word1:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_bfe_i32 v0, v0, 0, 16
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX12-NEXT: v_cvt_pk_f32_bf8_e64 v[0:1], v0 op_sel:[1,0]
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%a.sext = sext i16 %a to i32
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%ret = tail call <2 x float> @llvm.amdgcn.cvt.pk.f32.bf8(i32 %a.sext, i1 true)
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ret <2 x float> %ret
608+
}
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define <2 x float> @test_sext_cvt_pk_f32_fp8_word0(i16 %a) {
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; GFX940-LABEL: test_sext_cvt_pk_f32_fp8_word0:
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; GFX940: ; %bb.0:
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; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX940-NEXT: v_bfe_i32 v0, v0, 0, 16
615+
; GFX940-NEXT: v_cvt_pk_f32_fp8_e32 v[0:1], v0
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; GFX940-NEXT: s_setpc_b64 s[30:31]
617+
;
618+
; GFX12-LABEL: test_sext_cvt_pk_f32_fp8_word0:
619+
; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
621+
; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
623+
; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_bfe_i32 v0, v0, 0, 16
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX12-NEXT: v_cvt_pk_f32_fp8_e32 v[0:1], v0
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; GFX12-NEXT: s_setpc_b64 s[30:31]
629+
%a.sext = sext i16 %a to i32
630+
%ret = tail call <2 x float> @llvm.amdgcn.cvt.pk.f32.fp8(i32 %a.sext, i1 false)
631+
ret <2 x float> %ret
632+
}

‎llvm/test/CodeGen/AMDGPU/verifier-sdwa-cvt.mir

Lines changed: 38 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,38 @@
1+
# RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx940 -run-pass machineverifier -o /dev/null %s 2>&1 | FileCheck -implicit-check-not="Bad machine code" %s
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# CHECK: *** Bad machine code: sext, abs and neg are not allowed on this instruction ***
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# CHECK: $vgpr0 = V_CVT_F32_FP8_sdwa 1, $vgpr0, 0, 0, 4, implicit $mode, implicit $exec
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# CHECK: *** Bad machine code: sext, abs and neg are not allowed on this instruction ***
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# CHECK: $vgpr0 = V_CVT_F32_BF8_sdwa 1, $vgpr0, 0, 0, 4, implicit $mode, implicit $exec
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# CHECK: *** Bad machine code: sext, abs and neg are not allowed on this instruction ***
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# CHECK: $vgpr0_vgpr1 = V_CVT_PK_F32_FP8_sdwa 1, $vgpr0, 0, 0, 4, implicit $mode, implicit $exec
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# CHECK: *** Bad machine code: sext, abs and neg are not allowed on this instruction ***
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# CHECK: $vgpr0_vgpr1 = V_CVT_PK_F32_BF8_sdwa 1, $vgpr0, 0, 0, 4, implicit $mode, implicit $exec
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# CHECK: *** Bad machine code: sext, abs and neg are not allowed on this instruction ***
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# CHECK: $vgpr0 = V_CVT_F32_FP8_sdwa 2, $vgpr0, 0, 0, 4, implicit $mode, implicit $exec
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# CHECK: *** Bad machine code: sext, abs and neg are not allowed on this instruction ***
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# CHECK: $vgpr0 = V_CVT_F32_BF8_sdwa 2, $vgpr0, 0, 0, 4, implicit $mode, implicit $exec
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# CHECK: *** Bad machine code: sext, abs and neg are not allowed on this instruction ***
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# CHECK: $vgpr0_vgpr1 = V_CVT_PK_F32_FP8_sdwa 2, $vgpr0, 0, 0, 4, implicit $mode, implicit $exec
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# CHECK: *** Bad machine code: sext, abs and neg are not allowed on this instruction ***
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# CHECK: $vgpr0_vgpr1 = V_CVT_PK_F32_BF8_sdwa 2, $vgpr0, 0, 0, 4, implicit $mode, implicit $exec
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---
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name: test
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liveins:
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body: |
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bb.0:
25+
liveins: $vgpr0, $vgpr0_vgpr1
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; sext/neg
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$vgpr0 = V_CVT_F32_FP8_sdwa 1, $vgpr0, 0, 0, 4, implicit $mode, implicit $exec
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$vgpr0 = V_CVT_F32_BF8_sdwa 1, $vgpr0, 0, 0, 4, implicit $mode, implicit $exec
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$vgpr0_vgpr1 = V_CVT_PK_F32_FP8_sdwa 1, $vgpr0, 0, 0, 4, implicit $mode, implicit $exec
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$vgpr0_vgpr1 = V_CVT_PK_F32_BF8_sdwa 1, $vgpr0, 0, 0, 4, implicit $mode, implicit $exec
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; abs
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$vgpr0 = V_CVT_F32_FP8_sdwa 2, $vgpr0, 0, 0, 4, implicit $mode, implicit $exec
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$vgpr0 = V_CVT_F32_BF8_sdwa 2, $vgpr0, 0, 0, 4, implicit $mode, implicit $exec
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$vgpr0_vgpr1 = V_CVT_PK_F32_FP8_sdwa 2, $vgpr0, 0, 0, 4, implicit $mode, implicit $exec
37+
$vgpr0_vgpr1 = V_CVT_PK_F32_BF8_sdwa 2, $vgpr0, 0, 0, 4, implicit $mode, implicit $exec
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...

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