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[RISCV] Add commutable tests for fixed-point instructions
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‎llvm/test/CodeGen/RISCV/rvv/commutable.ll

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@@ -649,3 +649,178 @@ entry:
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ret <vscale x 1 x i64> %ret
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}
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; vsadd.vv
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declare <vscale x 1 x i64> @llvm.riscv.vsadd.nxv1i64.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, iXLen);
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define <vscale x 1 x i64> @commutable_vsadd_vv(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {
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; CHECK-LABEL: commutable_vsadd_vv:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
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; CHECK-NEXT: vsadd.vv v10, v8, v9
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; CHECK-NEXT: vsadd.vv v8, v9, v8
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; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v8
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i64> @llvm.riscv.vsadd.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2)
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%b = call <vscale x 1 x i64> @llvm.riscv.vsadd.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %1, <vscale x 1 x i64> %0, iXLen %2)
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%ret = add <vscale x 1 x i64> %a, %b
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ret <vscale x 1 x i64> %ret
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}
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declare <vscale x 1 x i64> @llvm.riscv.vsadd.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, iXLen, iXLen);
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define <vscale x 1 x i64> @commutable_vsadd_vv_masked(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %mask, iXLen %2) {
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; CHECK-LABEL: commutable_vsadd_vv_masked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
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; CHECK-NEXT: vsadd.vv v10, v8, v9, v0.t
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; CHECK-NEXT: vsadd.vv v8, v9, v8, v0.t
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; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v8
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; CHECK-NEXT: ret
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%a = call <vscale x 1 x i64> @llvm.riscv.vsadd.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %mask, iXLen %2, iXLen 1)
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%b = call <vscale x 1 x i64> @llvm.riscv.vsadd.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %1, <vscale x 1 x i64> %0, <vscale x 1 x i1> %mask, iXLen %2, iXLen 1)
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%ret = add <vscale x 1 x i64> %a, %b
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ret <vscale x 1 x i64> %ret
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}
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; vsaddu.vv
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declare <vscale x 1 x i64> @llvm.riscv.vsaddu.nxv1i64.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, iXLen);
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define <vscale x 1 x i64> @commutable_vsaddu_vv(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {
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; CHECK-LABEL: commutable_vsaddu_vv:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
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; CHECK-NEXT: vsaddu.vv v10, v8, v9
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; CHECK-NEXT: vsaddu.vv v8, v9, v8
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; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v8
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i64> @llvm.riscv.vsaddu.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2)
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%b = call <vscale x 1 x i64> @llvm.riscv.vsaddu.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %1, <vscale x 1 x i64> %0, iXLen %2)
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%ret = add <vscale x 1 x i64> %a, %b
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ret <vscale x 1 x i64> %ret
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}
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declare <vscale x 1 x i64> @llvm.riscv.vsaddu.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, iXLen, iXLen);
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define <vscale x 1 x i64> @commutable_vsaddu_vv_masked(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %mask, iXLen %2) {
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; CHECK-LABEL: commutable_vsaddu_vv_masked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
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; CHECK-NEXT: vsaddu.vv v10, v8, v9, v0.t
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; CHECK-NEXT: vsaddu.vv v8, v9, v8, v0.t
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; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v8
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; CHECK-NEXT: ret
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%a = call <vscale x 1 x i64> @llvm.riscv.vsaddu.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %mask, iXLen %2, iXLen 1)
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%b = call <vscale x 1 x i64> @llvm.riscv.vsaddu.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %1, <vscale x 1 x i64> %0, <vscale x 1 x i1> %mask, iXLen %2, iXLen 1)
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%ret = add <vscale x 1 x i64> %a, %b
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ret <vscale x 1 x i64> %ret
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}
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; vaadd.vv
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declare <vscale x 1 x i64> @llvm.riscv.vaadd.nxv1i64.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, iXLen, iXLen);
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define <vscale x 1 x i64> @commutable_vaadd_vv(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {
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; CHECK-LABEL: commutable_vaadd_vv:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
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; CHECK-NEXT: csrwi vxrm, 0
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; CHECK-NEXT: vaadd.vv v10, v8, v9
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; CHECK-NEXT: vaadd.vv v8, v9, v8
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; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v8
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i64> @llvm.riscv.vaadd.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen 0, iXLen %2)
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%b = call <vscale x 1 x i64> @llvm.riscv.vaadd.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %1, <vscale x 1 x i64> %0, iXLen 0, iXLen %2)
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%ret = add <vscale x 1 x i64> %a, %b
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ret <vscale x 1 x i64> %ret
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}
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declare <vscale x 1 x i64> @llvm.riscv.vaadd.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, iXLen, iXLen, iXLen);
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define <vscale x 1 x i64> @commutable_vaadd_vv_masked(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %mask, iXLen %2) {
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; CHECK-LABEL: commutable_vaadd_vv_masked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
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; CHECK-NEXT: csrwi vxrm, 0
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; CHECK-NEXT: vaadd.vv v10, v8, v9, v0.t
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; CHECK-NEXT: vaadd.vv v8, v9, v8, v0.t
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; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v8
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; CHECK-NEXT: ret
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%a = call <vscale x 1 x i64> @llvm.riscv.vaadd.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %mask, iXLen 0, iXLen %2, iXLen 1)
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%b = call <vscale x 1 x i64> @llvm.riscv.vaadd.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %1, <vscale x 1 x i64> %0, <vscale x 1 x i1> %mask, iXLen 0, iXLen %2, iXLen 1)
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%ret = add <vscale x 1 x i64> %a, %b
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ret <vscale x 1 x i64> %ret
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}
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; vaaddu.vv
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declare <vscale x 1 x i64> @llvm.riscv.vaaddu.nxv1i64.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, iXLen, iXLen);
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define <vscale x 1 x i64> @commutable_vaaddu_vv(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {
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; CHECK-LABEL: commutable_vaaddu_vv:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
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; CHECK-NEXT: csrwi vxrm, 0
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; CHECK-NEXT: vaaddu.vv v10, v8, v9
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; CHECK-NEXT: vaaddu.vv v8, v9, v8
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; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v8
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i64> @llvm.riscv.vaaddu.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen 0, iXLen %2)
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%b = call <vscale x 1 x i64> @llvm.riscv.vaaddu.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %1, <vscale x 1 x i64> %0, iXLen 0, iXLen %2)
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%ret = add <vscale x 1 x i64> %a, %b
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ret <vscale x 1 x i64> %ret
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}
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declare <vscale x 1 x i64> @llvm.riscv.vaaddu.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, iXLen, iXLen, iXLen);
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define <vscale x 1 x i64> @commutable_vaaddu_vv_masked(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %mask, iXLen %2) {
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; CHECK-LABEL: commutable_vaaddu_vv_masked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
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; CHECK-NEXT: csrwi vxrm, 0
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; CHECK-NEXT: vaaddu.vv v10, v8, v9, v0.t
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; CHECK-NEXT: vaaddu.vv v8, v9, v8, v0.t
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; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v8
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; CHECK-NEXT: ret
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%a = call <vscale x 1 x i64> @llvm.riscv.vaaddu.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %mask, iXLen 0, iXLen %2, iXLen 1)
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%b = call <vscale x 1 x i64> @llvm.riscv.vaaddu.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %1, <vscale x 1 x i64> %0, <vscale x 1 x i1> %mask, iXLen 0, iXLen %2, iXLen 1)
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%ret = add <vscale x 1 x i64> %a, %b
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ret <vscale x 1 x i64> %ret
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}
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; vsmul.vv
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declare <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, iXLen, iXLen);
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define <vscale x 1 x i64> @commutable_vsmul_vv(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {
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; CHECK-LABEL: commutable_vsmul_vv:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
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; CHECK-NEXT: csrwi vxrm, 0
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; CHECK-NEXT: vsmul.vv v10, v8, v9
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; CHECK-NEXT: vsmul.vv v8, v9, v8
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; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v8
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen 0, iXLen %2)
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%b = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %1, <vscale x 1 x i64> %0, iXLen 0, iXLen %2)
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%ret = add <vscale x 1 x i64> %a, %b
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ret <vscale x 1 x i64> %ret
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}
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declare <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, iXLen, iXLen, iXLen);
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define <vscale x 1 x i64> @commutable_vsmul_vv_masked(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %mask, iXLen %2) {
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; CHECK-LABEL: commutable_vsmul_vv_masked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
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; CHECK-NEXT: csrwi vxrm, 0
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; CHECK-NEXT: vsmul.vv v10, v8, v9, v0.t
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; CHECK-NEXT: vsmul.vv v8, v9, v8, v0.t
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; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v8
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; CHECK-NEXT: ret
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%a = call <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %mask, iXLen 0, iXLen %2, iXLen 1)
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%b = call <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %1, <vscale x 1 x i64> %0, <vscale x 1 x i1> %mask, iXLen 0, iXLen %2, iXLen 1)
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%ret = add <vscale x 1 x i64> %a, %b
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ret <vscale x 1 x i64> %ret
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}

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