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[RISCV] Modify register type of extd* Xqcibm instructions (#134027)
The v0.8 spec specifies that rs1 cannot be x31 (t6) since these instructions operate on a pair of registers (rs1 and rs1 + 1) with no wrap around. The latest spec can be found here: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.8.0
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6 files changed

+61
-20
lines changed

6 files changed

+61
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lines changed

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -197,6 +197,16 @@ DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint32_t Address,
197197
return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder);
198198
}
199199

200+
static DecodeStatus DecodeGPRNoX31RegisterClass(MCInst &Inst, uint32_t RegNo,
201+
uint64_t Address,
202+
const MCDisassembler *Decoder) {
203+
if (RegNo == 31) {
204+
return MCDisassembler::Fail;
205+
}
206+
207+
return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
208+
}
209+
200210
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo,
201211
uint64_t Address,
202212
const MCDisassembler *Decoder) {

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -584,15 +584,15 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
584584
def QC_INSBPR : QCIRVInstRR<0b00010, GPR, "qc.insbpr">;
585585
def QC_INSBPRH : QCIRVInstRR<0b00011, GPR, "qc.insbprh">;
586586
def QC_EXTU : QCIBitManipRII<0b010, 0b00, GPRNoX0, "qc.extu">;
587-
def QC_EXTDU : QCIBitManipRII<0b010, 0b10, GPR, "qc.extdu">;
588-
def QC_EXTDUR : QCIRVInstRR<0b00100, GPR, "qc.extdur">;
589-
def QC_EXTDUPR : QCIRVInstRR<0b00110, GPR, "qc.extdupr">;
590-
def QC_EXTDUPRH : QCIRVInstRR<0b00111, GPR, "qc.extduprh">;
587+
def QC_EXTDU : QCIBitManipRII<0b010, 0b10, GPRNoX31, "qc.extdu">;
588+
def QC_EXTDUR : QCIRVInstRR<0b00100, GPRNoX31, "qc.extdur">;
589+
def QC_EXTDUPR : QCIRVInstRR<0b00110, GPRNoX31, "qc.extdupr">;
590+
def QC_EXTDUPRH : QCIRVInstRR<0b00111, GPRNoX31, "qc.extduprh">;
591591
def QC_EXT : QCIBitManipRII<0b010, 0b01, GPRNoX0, "qc.ext">;
592-
def QC_EXTD : QCIBitManipRII<0b010, 0b11, GPR, "qc.extd">;
593-
def QC_EXTDR : QCIRVInstRR<0b00101, GPR, "qc.extdr">;
594-
def QC_EXTDPR : QCIRVInstRR<0b01000, GPR, "qc.extdpr">;
595-
def QC_EXTDPRH : QCIRVInstRR<0b01001, GPR, "qc.extdprh">;
592+
def QC_EXTD : QCIBitManipRII<0b010, 0b11, GPRNoX31, "qc.extd">;
593+
def QC_EXTDR : QCIRVInstRR<0b00101, GPRNoX31, "qc.extdr">;
594+
def QC_EXTDPR : QCIRVInstRR<0b01000, GPRNoX31, "qc.extdpr">;
595+
def QC_EXTDPRH : QCIRVInstRR<0b01001, GPRNoX31, "qc.extdprh">;
596596
def QC_COMPRESS2 : QCIRVInstI<0b0000, "qc.compress2">;
597597
def QC_COMPRESS3 : QCIRVInstI<0b0001, "qc.compress3">;
598598
def QC_EXPAND2 : QCIRVInstI<0b0010, "qc.expand2">;

‎llvm/lib/Target/RISCV/RISCVRegisterInfo.td

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -302,6 +302,11 @@ def GPRX1X5 : GPRRegisterClass<(add X1, X5)> {
302302
let DiagnosticString = "register must be ra or t0 (x1 or x5)";
303303
}
304304

305+
def GPRNoX31 : GPRRegisterClass<(sub GPR, X31)> {
306+
let DiagnosticType = "InvalidRegClassGPRX31";
307+
let DiagnosticString = "register must be a GPR excluding t6 (x31)";
308+
}
309+
305310
//===----------------------------------------------------------------------===//
306311
// Even-Odd GPR Pairs
307312
//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-zve64f.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ body: |
2424
; CHECK-NEXT: renamable $v8 = PseudoVLE64_V_M1 undef renamable $v8, [[COPY1]], 1, 6 /* e64 */, 2 /* tu, ma */, implicit $vl, implicit $vtype :: (load unknown-size, align 8)
2525
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 8, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
2626
; CHECK-NEXT: renamable $v9 = PseudoVLE32_V_M1 undef renamable $v9, [[COPY]], 8, 5 /* e32 */, 2 /* tu, ma */, implicit $vl, implicit $vtype :: (load unknown-size, align 4)
27-
; CHECK-NEXT: INLINEASM &"# use $0 $1 $2 $3", 1 /* sideeffect attdialect */, 3145737 /* reguse:VR */, killed renamable $v10, 3145737 /* reguse:VR */, killed renamable $v11, 3145737 /* reguse:VR */, killed renamable $v8, 3145737 /* reguse:VR */, killed renamable $v9
27+
; CHECK-NEXT: INLINEASM &"# use $0 $1 $2 $3", 1 /* sideeffect attdialect */, 3997705 /* reguse:VR */, killed renamable $v10, 3997705 /* reguse:VR */, killed renamable $v11, 3997705 /* reguse:VR */, killed renamable $v8, 3997705 /* reguse:VR */, killed renamable $v9
2828
; CHECK-NEXT: PseudoRET
2929
%3:gpr = COPY $x12
3030
%2:gpr = COPY $x11
@@ -34,7 +34,7 @@ body: |
3434
renamable $v11 = PseudoVMV_S_X undef renamable $v11, %1, 8, 5 /* e32 */
3535
renamable $v8 = PseudoVLE64_V_M1 undef renamable $v8, %2, 1, 6 /* e64 */, 2 /* tu, ma */ :: (load unknown-size, align 8)
3636
renamable $v9 = PseudoVLE32_V_M1 undef renamable $v9, %3, 8, 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size, align 4)
37-
INLINEASM &"# use $0 $1 $2 $3", 1 /* sideeffect attdialect */, 3145737 /* reguse:VR */, killed renamable $v10, 3145737 /* reguse:VR */, killed renamable $v11, 3145737 /* reguse:VR */, killed renamable $v8, 3145737 /* reguse:VR */, killed renamable $v9
37+
INLINEASM &"# use $0 $1 $2 $3", 1 /* sideeffect attdialect */, 3997705 /* reguse:VR */, killed renamable $v10, 3997705 /* reguse:VR */, killed renamable $v11, 3997705 /* reguse:VR */, killed renamable $v8, 3997705 /* reguse:VR */, killed renamable $v9
3838
PseudoRET
3939
4040
...

‎llvm/test/MC/RISCV/xqcibm-invalid.s

Lines changed: 33 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -269,7 +269,8 @@ qc.ext x27, x6, 31, 41
269269
qc.ext x27, x6, 31, 1
270270

271271

272-
# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction
272+
# CHECK-PLUS: :[[@LINE+2]]:14: error: register must be a GPR excluding t6 (x31)
273+
# CHECK-MINUS: :[[@LINE+1]]:14: error: invalid operand for instruction
273274
qc.extdu x1, 8, 8, 8
274275

275276
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
@@ -289,7 +290,8 @@ qc.extdu x1, x8, 8, 78
289290
qc.extdu x1, x8, 8, 8
290291

291292

292-
# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction
293+
# CHECK-PLUS: :[[@LINE+2]]:14: error: register must be a GPR excluding t6 (x31)
294+
# CHECK-MINUS: :[[@LINE+1]]:14: error: invalid operand for instruction
293295
qc.extd x13, 21, 10, 15
294296

295297
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
@@ -396,6 +398,10 @@ qc.extdur x9, x19
396398
# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction
397399
qc.extdur x0, x19, x29
398400

401+
# CHECK-PLUS: :[[@LINE+2]]:15: error: register must be a GPR excluding t6 (x31)
402+
# CHECK-MINUS: :[[@LINE+1]]:15: error: invalid operand for instruction
403+
qc.extdur x9, x31, x29
404+
399405
# CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero (x0)
400406
# CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction
401407
qc.extdur x9, x19, x0
@@ -406,21 +412,25 @@ qc.extdur x9, x19, x29
406412

407413
# CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero (x0)
408414
# CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction
409-
qc.extdr x12, x31, 30
415+
qc.extdr x12, x29, 30
410416

411417
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
412-
qc.extdr x12, x31
418+
qc.extdr x12, x29
413419

414420
# CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR excluding zero (x0)
415421
# CHECK-MINUS: :[[@LINE+1]]:10: error: invalid operand for instruction
416-
qc.extdr x0, x31, x30
422+
qc.extdr x0, x29, x30
423+
424+
# CHECK-PLUS: :[[@LINE+2]]:15: error: register must be a GPR excluding t6 (x31)
425+
# CHECK-MINUS: :[[@LINE+1]]:15: error: invalid operand for instruction
426+
qc.extdr x12, x31, x30
417427

418428
# CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero (x0)
419429
# CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction
420-
qc.extdr x12, x31, x0
430+
qc.extdr x12, x29, x0
421431

422432
# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcibm' (Qualcomm uC Bit Manipulation Extension)
423-
qc.extdr x12, x31, x30
433+
qc.extdr x12, x29, x30
424434

425435

426436
# CHECK-PLUS: :[[@LINE+2]]:22: error: register must be a GPR excluding zero (x0)
@@ -434,6 +444,10 @@ qc.extdupr x13, x23
434444
# CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction
435445
qc.extdupr x0, x23, x3
436446

447+
# CHECK-PLUS: :[[@LINE+2]]:17: error: register must be a GPR excluding t6 (x31)
448+
# CHECK-MINUS: :[[@LINE+1]]:17: error: invalid operand for instruction
449+
qc.extdupr x13, x31, x3
450+
437451
# CHECK-PLUS: :[[@LINE+2]]:22: error: register must be a GPR excluding zero (x0)
438452
# CHECK-MINUS: :[[@LINE+1]]:22: error: invalid operand for instruction
439453
qc.extdupr x13, x23, x0
@@ -453,6 +467,10 @@ qc.extduprh x18, x8
453467
# CHECK-MINUS: :[[@LINE+1]]:13: error: invalid operand for instruction
454468
qc.extduprh x0, x8, x9
455469

470+
# CHECK-PLUS: :[[@LINE+2]]:18: error: register must be a GPR excluding t6 (x31)
471+
# CHECK-MINUS: :[[@LINE+1]]:18: error: invalid operand for instruction
472+
qc.extduprh x18, x31, x9
473+
456474
# CHECK-PLUS: :[[@LINE+2]]:22: error: register must be a GPR excluding zero (x0)
457475
# CHECK-MINUS: :[[@LINE+1]]:22: error: invalid operand for instruction
458476
qc.extduprh x18, x8, x0
@@ -472,6 +490,10 @@ qc.extdpr x1, x4
472490
# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction
473491
qc.extdpr x0, x4, x15
474492

493+
# CHECK-PLUS: :[[@LINE+2]]:15: error: register must be a GPR excluding t6 (x31)
494+
# CHECK-MINUS: :[[@LINE+1]]:15: error: invalid operand for instruction
495+
qc.extdpr x1, x31, x15
496+
475497
# CHECK-PLUS: :[[@LINE+2]]:19: error: register must be a GPR excluding zero (x0)
476498
# CHECK-MINUS: :[[@LINE+1]]:19: error: invalid operand for instruction
477499
qc.extdpr x1, x4, x0
@@ -491,6 +513,10 @@ qc.extdprh x6, x24
491513
# CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction
492514
qc.extdprh x0, x24, x25
493515

516+
# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding t6 (x31)
517+
# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction
518+
qc.extdprh x6, x31, x25
519+
494520
# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero (x0)
495521
# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction
496522
qc.extdprh x6, x24, x0

‎llvm/test/MC/RISCV/xqcibm-valid.s

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -90,9 +90,9 @@ qc.insbprh x2, x3, x11
9090
# CHECK-ENC: encoding: [0x8b,0xb4,0xd9,0x09]
9191
qc.extdur x9, x19, x29
9292

93-
# CHECK-INST: qc.extdr a2, t6, t5
94-
# CHECK-ENC: encoding: [0x0b,0xb6,0xef,0x0b]
95-
qc.extdr x12, x31, x30
93+
# CHECK-INST: qc.extdr a2, t4, t5
94+
# CHECK-ENC: encoding: [0x0b,0xb6,0xee,0x0b]
95+
qc.extdr x12, x29, x30
9696

9797
# CHECK-INST: qc.extdupr a3, s7, gp
9898
# CHECK-ENC: encoding: [0x8b,0xb6,0x3b,0x0c]

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