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[mips] Print instructions "beq", "bne" and "or" using assembler pseudo
instructions "beqz", "bnez" and "move", when possible. beq $2, $zero, $L1 => beqz $2, $L1 bne $2, $zero, $L1 => bnez $2, $L1 or $2, $3, $zero => move $2, $3 llvm-svn: 187229
1 parent 1e01014 commit 53900e5

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8 files changed

+92
-32
lines changed

8 files changed

+92
-32
lines changed

‎llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp

Lines changed: 51 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,12 @@ using namespace llvm;
2626
#define PRINT_ALIAS_INSTR
2727
#include "MipsGenAsmWriter.inc"
2828

29+
template<unsigned R>
30+
static bool isReg(const MCInst &MI, unsigned OpNo) {
31+
assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
32+
return MI.getOperand(OpNo).getReg() == R;
33+
}
34+
2935
const char* Mips::MipsFCCToString(Mips::CondCode CC) {
3036
switch (CC) {
3137
case FCOND_F:
@@ -80,7 +86,7 @@ void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
8086
}
8187

8288
// Try to print any aliases first.
83-
if (!printAliasInstr(MI, O))
89+
if (!printAliasInstr(MI, O) && !printAlias(*MI, O))
8490
printInstruction(MI, O);
8591
printAnnotation(O, Annot);
8692

@@ -209,3 +215,47 @@ printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) {
209215
const MCOperand& MO = MI->getOperand(opNum);
210216
O << MipsFCCToString((Mips::CondCode)MO.getImm());
211217
}
218+
219+
bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
220+
unsigned OpNo, raw_ostream &OS) {
221+
OS << "\t" << Str << "\t";
222+
printOperand(&MI, OpNo, OS);
223+
return true;
224+
}
225+
226+
bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
227+
unsigned OpNo0, unsigned OpNo1,
228+
raw_ostream &OS) {
229+
printAlias(Str, MI, OpNo0, OS);
230+
OS << ", ";
231+
printOperand(&MI, OpNo1, OS);
232+
return true;
233+
}
234+
235+
bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) {
236+
switch (MI.getOpcode()) {
237+
case Mips::BEQ:
238+
if (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS))
239+
return true;
240+
break;
241+
case Mips::BEQ64:
242+
if (isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS))
243+
return true;
244+
break;
245+
case Mips::BNE:
246+
if (isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS))
247+
return true;
248+
break;
249+
case Mips::BNE64:
250+
if (isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS))
251+
return true;
252+
break;
253+
case Mips::OR:
254+
if (isReg<Mips::ZERO>(MI, 2) && printAlias("move", MI, 0, 1, OS))
255+
return true;
256+
break;
257+
default: return false;
258+
}
259+
260+
return false;
261+
}

‎llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,12 @@ class MipsInstPrinter : public MCInstPrinter {
9797
void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O);
9898
void printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O);
9999
void printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O);
100+
101+
bool printAlias(const char *Str, const MCInst &MI, unsigned OpNo,
102+
raw_ostream &OS);
103+
bool printAlias(const char *Str, const MCInst &MI, unsigned OpNo0,
104+
unsigned OpNo1, raw_ostream &OS);
105+
bool printAlias(const MCInst &MI, raw_ostream &OS);
100106
};
101107
} // end namespace llvm
102108

‎llvm/test/CodeGen/Mips/atomic.ll

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -14,15 +14,15 @@ entry:
1414
; CHECK-EL: ll $[[R1:[0-9]+]], 0($[[R0]])
1515
; CHECK-EL: addu $[[R2:[0-9]+]], $[[R1]], $4
1616
; CHECK-EL: sc $[[R2]], 0($[[R0]])
17-
; CHECK-EL: beq $[[R2]], $zero, $[[BB0]]
17+
; CHECK-EL: beqz $[[R2]], $[[BB0]]
1818

1919
; CHECK-EB-LABEL: AtomicLoadAdd32:
2020
; CHECK-EB: lw $[[R0:[0-9]+]], %got(x)
2121
; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:
2222
; CHECK-EB: ll $[[R1:[0-9]+]], 0($[[R0]])
2323
; CHECK-EB: addu $[[R2:[0-9]+]], $[[R1]], $4
2424
; CHECK-EB: sc $[[R2]], 0($[[R0]])
25-
; CHECK-EB: beq $[[R2]], $zero, $[[BB0]]
25+
; CHECK-EB: beqz $[[R2]], $[[BB0]]
2626
}
2727

2828
define i32 @AtomicLoadNand32(i32 %incr) nounwind {
@@ -37,7 +37,7 @@ entry:
3737
; CHECK-EL: and $[[R3:[0-9]+]], $[[R1]], $4
3838
; CHECK-EL: nor $[[R2:[0-9]+]], $zero, $[[R3]]
3939
; CHECK-EL: sc $[[R2]], 0($[[R0]])
40-
; CHECK-EL: beq $[[R2]], $zero, $[[BB0]]
40+
; CHECK-EL: beqz $[[R2]], $[[BB0]]
4141

4242
; CHECK-EB-LABEL: AtomicLoadNand32:
4343
; CHECK-EB: lw $[[R0:[0-9]+]], %got(x)
@@ -46,7 +46,7 @@ entry:
4646
; CHECK-EB: and $[[R3:[0-9]+]], $[[R1]], $4
4747
; CHECK-EB: nor $[[R2:[0-9]+]], $zero, $[[R3]]
4848
; CHECK-EB: sc $[[R2]], 0($[[R0]])
49-
; CHECK-EB: beq $[[R2]], $zero, $[[BB0]]
49+
; CHECK-EB: beqz $[[R2]], $[[BB0]]
5050
}
5151

5252
define i32 @AtomicSwap32(i32 %newval) nounwind {
@@ -62,14 +62,14 @@ entry:
6262
; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:
6363
; CHECK-EL: ll ${{[0-9]+}}, 0($[[R0]])
6464
; CHECK-EL: sc $[[R2:[0-9]+]], 0($[[R0]])
65-
; CHECK-EL: beq $[[R2]], $zero, $[[BB0]]
65+
; CHECK-EL: beqz $[[R2]], $[[BB0]]
6666

6767
; CHECK-EB-LABEL: AtomicSwap32:
6868
; CHECK-EB: lw $[[R0:[0-9]+]], %got(x)
6969
; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:
7070
; CHECK-EB: ll ${{[0-9]+}}, 0($[[R0]])
7171
; CHECK-EB: sc $[[R2:[0-9]+]], 0($[[R0]])
72-
; CHECK-EB: beq $[[R2]], $zero, $[[BB0]]
72+
; CHECK-EB: beqz $[[R2]], $[[BB0]]
7373
}
7474

7575
define i32 @AtomicCmpSwap32(i32 %oldval, i32 %newval) nounwind {
@@ -86,7 +86,7 @@ entry:
8686
; CHECK-EL: ll $2, 0($[[R0]])
8787
; CHECK-EL: bne $2, $4, $[[BB1:[A-Z_0-9]+]]
8888
; CHECK-EL: sc $[[R2:[0-9]+]], 0($[[R0]])
89-
; CHECK-EL: beq $[[R2]], $zero, $[[BB0]]
89+
; CHECK-EL: beqz $[[R2]], $[[BB0]]
9090
; CHECK-EL: $[[BB1]]:
9191

9292
; CHECK-EB-LABEL: AtomicCmpSwap32:
@@ -95,7 +95,7 @@ entry:
9595
; CHECK-EB: ll $2, 0($[[R0]])
9696
; CHECK-EB: bne $2, $4, $[[BB1:[A-Z_0-9]+]]
9797
; CHECK-EB: sc $[[R2:[0-9]+]], 0($[[R0]])
98-
; CHECK-EB: beq $[[R2]], $zero, $[[BB0]]
98+
; CHECK-EB: beqz $[[R2]], $[[BB0]]
9999
; CHECK-EB: $[[BB1]]:
100100
}
101101

@@ -126,7 +126,7 @@ entry:
126126
; CHECK-EL: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
127127
; CHECK-EL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
128128
; CHECK-EL: sc $[[R14]], 0($[[R2]])
129-
; CHECK-EL: beq $[[R14]], $zero, $[[BB0]]
129+
; CHECK-EL: beqz $[[R14]], $[[BB0]]
130130

131131
; CHECK-EL: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
132132
; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
@@ -152,7 +152,7 @@ entry:
152152
; CHECK-EB: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
153153
; CHECK-EB: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
154154
; CHECK-EB: sc $[[R14]], 0($[[R2]])
155-
; CHECK-EB: beq $[[R14]], $zero, $[[BB0]]
155+
; CHECK-EB: beqz $[[R14]], $[[BB0]]
156156

157157
; CHECK-EB: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
158158
; CHECK-EB: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
@@ -183,7 +183,7 @@ entry:
183183
; CHECK-EL: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
184184
; CHECK-EL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
185185
; CHECK-EL: sc $[[R14]], 0($[[R2]])
186-
; CHECK-EL: beq $[[R14]], $zero, $[[BB0]]
186+
; CHECK-EL: beqz $[[R14]], $[[BB0]]
187187

188188
; CHECK-EL: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
189189
; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
@@ -209,7 +209,7 @@ entry:
209209
; CHECK-EB: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
210210
; CHECK-EB: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
211211
; CHECK-EB: sc $[[R14]], 0($[[R2]])
212-
; CHECK-EB: beq $[[R14]], $zero, $[[BB0]]
212+
; CHECK-EB: beqz $[[R14]], $[[BB0]]
213213

214214
; CHECK-EB: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
215215
; CHECK-EB: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
@@ -241,7 +241,7 @@ entry:
241241
; CHECK-EL: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
242242
; CHECK-EL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
243243
; CHECK-EL: sc $[[R14]], 0($[[R2]])
244-
; CHECK-EL: beq $[[R14]], $zero, $[[BB0]]
244+
; CHECK-EL: beqz $[[R14]], $[[BB0]]
245245

246246
; CHECK-EL: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
247247
; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
@@ -268,7 +268,7 @@ entry:
268268
; CHECK-EB: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
269269
; CHECK-EB: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
270270
; CHECK-EB: sc $[[R14]], 0($[[R2]])
271-
; CHECK-EB: beq $[[R14]], $zero, $[[BB0]]
271+
; CHECK-EB: beqz $[[R14]], $[[BB0]]
272272

273273
; CHECK-EB: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
274274
; CHECK-EB: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
@@ -298,7 +298,7 @@ entry:
298298
; CHECK-EL: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
299299
; CHECK-EL: or $[[R14:[0-9]+]], $[[R13]], $[[R18]]
300300
; CHECK-EL: sc $[[R14]], 0($[[R2]])
301-
; CHECK-EL: beq $[[R14]], $zero, $[[BB0]]
301+
; CHECK-EL: beqz $[[R14]], $[[BB0]]
302302

303303
; CHECK-EL: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
304304
; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
@@ -323,7 +323,7 @@ entry:
323323
; CHECK-EB: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
324324
; CHECK-EB: or $[[R14:[0-9]+]], $[[R13]], $[[R18]]
325325
; CHECK-EB: sc $[[R14]], 0($[[R2]])
326-
; CHECK-EB: beq $[[R14]], $zero, $[[BB0]]
326+
; CHECK-EB: beqz $[[R14]], $[[BB0]]
327327

328328
; CHECK-EB: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
329329
; CHECK-EB: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
@@ -358,7 +358,7 @@ entry:
358358
; CHECK-EL: and $[[R14:[0-9]+]], $[[R12]], $[[R7]]
359359
; CHECK-EL: or $[[R15:[0-9]+]], $[[R14]], $[[R11]]
360360
; CHECK-EL: sc $[[R15]], 0($[[R2]])
361-
; CHECK-EL: beq $[[R15]], $zero, $[[BB0]]
361+
; CHECK-EL: beqz $[[R15]], $[[BB0]]
362362

363363
; CHECK-EL: $[[BB1]]:
364364
; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R13]], $[[R4]]
@@ -388,7 +388,7 @@ entry:
388388
; CHECK-EB: and $[[R15:[0-9]+]], $[[R13]], $[[R8]]
389389
; CHECK-EB: or $[[R16:[0-9]+]], $[[R15]], $[[R12]]
390390
; CHECK-EB: sc $[[R16]], 0($[[R2]])
391-
; CHECK-EB: beq $[[R16]], $zero, $[[BB0]]
391+
; CHECK-EB: beqz $[[R16]], $[[BB0]]
392392

393393
; CHECK-EB: $[[BB1]]:
394394
; CHECK-EB: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]]

‎llvm/test/CodeGen/Mips/brdelayslot.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -133,7 +133,7 @@ declare void @foo11()
133133
; SUCCBB-LABEL: succbbs_loop1:
134134
; SUCCBB: blez $5, $BB
135135
; SUCCBB-NEXT: addiu
136-
; SUCCBB: bne ${{[0-9]+}}, $zero, $BB
136+
; SUCCBB: bnez ${{[0-9]+}}, $BB
137137
; SUCCBB-NEXT: addiu
138138

139139
define i32 @succbbs_loop1(i32* nocapture %a, i32 %n) {
@@ -159,7 +159,7 @@ for.end: ; preds = %for.body, %entry
159159
; Check that the first branch has its slot filled.
160160
;
161161
; SUCCBB-LABEL: succbbs_br1:
162-
; SUCCBB: beq ${{[0-9]+}}, $zero, $BB
162+
; SUCCBB: beqz ${{[0-9]+}}, $BB
163163
; SUCCBB-NEXT: lw $25, %call16(foo100)
164164

165165
define void @succbbs_br1(i32 %a) {

‎llvm/test/CodeGen/Mips/setcc-se.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ entry:
2424

2525
; CHECK-LABEL: slti_beq0:
2626
; CHECK: slti $[[R0:[0-9]+]], $4, -32768
27-
; CHECK: beq $[[R0]], $zero
27+
; CHECK: beqz $[[R0]]
2828

2929
define void @slti_beq0(i32 %a) {
3030
entry:
@@ -57,7 +57,7 @@ if.end:
5757

5858
; CHECK-LABEL: slti_beq2:
5959
; CHECK: slti $[[R0:[0-9]+]], $4, 32767
60-
; CHECK: beq $[[R0]], $zero
60+
; CHECK: beqz $[[R0]]
6161

6262
define void @slti_beq2(i32 %a) {
6363
entry:
@@ -90,7 +90,7 @@ if.end:
9090

9191
; CHECK-LABEL: sltiu_beq0:
9292
; CHECK: sltiu $[[R0:[0-9]+]], $4, 32767
93-
; CHECK: beq $[[R0]], $zero
93+
; CHECK: beqz $[[R0]]
9494

9595
define void @sltiu_beq0(i32 %a) {
9696
entry:
@@ -123,7 +123,7 @@ if.end:
123123

124124
; CHECK-LABEL: sltiu_beq2:
125125
; CHECK: sltiu $[[R0:[0-9]+]], $4, -32768
126-
; CHECK: beq $[[R0]], $zero
126+
; CHECK: beqz $[[R0]]
127127

128128
define void @sltiu_beq2(i32 %a) {
129129
entry:

‎llvm/test/MC/Disassembler/Mips/mips32_le.txt

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -260,6 +260,12 @@
260260
# CHECK: mov.s $f6, $f7
261261
0x86 0x39 0x00 0x46
262262

263+
# CHECK: move $7, $8
264+
0x21,0x38,0x00,0x01
265+
266+
# CHECK: move $3, $2
267+
0x25,0x18,0x40,0x00
268+
263269
# CHECK: msub $6, $7
264270
0x04 0x00 0xc7 0x70
265271

‎llvm/test/MC/Mips/mips-alu-instructions.s

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,6 @@
1313
# CHECK: ins $19, $9, 6, 7 # encoding: [0x84,0x61,0x33,0x7d]
1414
# CHECK: nor $9, $6, $7 # encoding: [0x27,0x48,0xc7,0x00]
1515
# CHECK: or $3, $3, $5 # encoding: [0x25,0x18,0x65,0x00]
16-
# CHECK: or $3, $2, $zero # encoding: [0x25,0x18,0x40,0x00]
1716
# CHECK: ori $4, $5, 17767 # encoding: [0x67,0x45,0xa4,0x34]
1817
# CHECK: ori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x34]
1918
# CHECK: ori $11, $11, 128 # encoding: [0x80,0x00,0x6b,0x35]
@@ -45,7 +44,6 @@
4544
ins $19, $9, 6,7
4645
nor $9, $6, $7
4746
or $3, $3, $5
48-
or $3, $2, $zero
4947
or $4, $5, 17767
5048
ori $9, $6, 17767
5149
ori $11, 128

‎llvm/test/MC/Mips/mips-jump-instructions.s

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | \
22
# RUN: FileCheck -check-prefix=CHECK32 %s
3-
# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips64r2 | \
3+
# RUN: llvm-mc %s -triple=mips64el-unknown-linux -show-encoding -mcpu=mips64r2 | \
44
# RUN: FileCheck -check-prefix=CHECK64 %s
55

66
# Check that the assembler can handle the documented syntax
@@ -28,9 +28,9 @@
2828
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
2929
# CHECK32: bal 1332 # encoding: [0x4d,0x01,0x11,0x04]
3030
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
31-
# CHECK32: bne $11, $zero, 1332 # encoding: [0x4d,0x01,0x60,0x15]
31+
# CHECK32: bnez $11, 1332 # encoding: [0x4d,0x01,0x60,0x15]
3232
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
33-
# CHECK32: beq $11, $zero, 1332 # encoding: [0x4d,0x01,0x60,0x11]
33+
# CHECK32: beqz $11, 1332 # encoding: [0x4d,0x01,0x60,0x11]
3434
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
3535

3636
# CHECK64: b 1332 # encoding: [0x4d,0x01,0x00,0x10]
@@ -53,9 +53,9 @@
5353
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
5454
# CHECK64: bal 1332 # encoding: [0x4d,0x01,0x11,0x04]
5555
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
56-
# CHECK64: bne $11, $zero, 1332 # encoding: [0x4d,0x01,0x60,0x15]
56+
# CHECK64: bnez $11, 1332 # encoding: [0x4d,0x01,0x60,0x15]
5757
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
58-
# CHECK64: beq $11, $zero, 1332 # encoding: [0x4d,0x01,0x60,0x11]
58+
# CHECK64: beqz $11, 1332 # encoding: [0x4d,0x01,0x60,0x11]
5959
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
6060

6161
.set noreorder

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