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[AMDGPU] Regenerate shift-and-i128-ubfe.ll test checks
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‎llvm/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll

Lines changed: 99 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -1,17 +1,28 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
12
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
23

34
; Extract the high bit of the 1st quarter
4-
; GCN-LABEL: {{^}}v_uextract_bit_31_i128:
5-
; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
6-
7-
; GCN: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}}
8-
; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO0]]{{$}}
9-
; GCN: v_mov_b32_e32 v[[ZERO2:[0-9]+]], v[[ZERO0]]{{$}}
10-
; GCN: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]]
11-
12-
; GCN: buffer_store_dwordx4 v{{\[}}[[SHIFT]]:[[ZERO2]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
13-
; GCN: s_endpgm
145
define amdgpu_kernel void @v_uextract_bit_31_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 {
6+
; GCN-LABEL: v_uextract_bit_31_i128:
7+
; GCN: ; %bb.0:
8+
; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
9+
; GCN-NEXT: s_ashr_i32 s3, s2, 31
10+
; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 4
11+
; GCN-NEXT: v_mov_b32_e32 v5, s1
12+
; GCN-NEXT: s_mov_b32 s7, 0xf000
13+
; GCN-NEXT: s_mov_b32 s6, 0
14+
; GCN-NEXT: s_waitcnt lgkmcnt(0)
15+
; GCN-NEXT: s_mov_b64 s[4:5], s[10:11]
16+
; GCN-NEXT: v_mov_b32_e32 v4, s0
17+
; GCN-NEXT: buffer_load_dword v0, v[4:5], s[4:7], 0 addr64
18+
; GCN-NEXT: v_mov_b32_e32 v1, 0
19+
; GCN-NEXT: v_mov_b32_e32 v2, v1
20+
; GCN-NEXT: s_mov_b64 s[10:11], s[6:7]
21+
; GCN-NEXT: v_mov_b32_e32 v3, v1
22+
; GCN-NEXT: s_waitcnt vmcnt(0)
23+
; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0
24+
; GCN-NEXT: buffer_store_dwordx4 v[0:3], v[4:5], s[8:11], 0 addr64
25+
; GCN-NEXT: s_endpgm
1526
%id.x = tail call i32 @llvm.amdgcn.workgroup.id.x()
1627
%in.gep = getelementptr i128, i128 addrspace(1)* %in, i32 %id.x
1728
%out.gep = getelementptr i128, i128 addrspace(1)* %out, i32 %id.x
@@ -23,18 +34,26 @@ define amdgpu_kernel void @v_uextract_bit_31_i128(i128 addrspace(1)* %out, i128
2334
}
2435

2536
; Extract the high bit of the 2nd quarter
26-
; GCN-LABEL: {{^}}v_uextract_bit_63_i128:
27-
; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
28-
29-
; GCN-DAG: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}}
30-
; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO0]]{{$}}
31-
; GCN: v_mov_b32_e32 v[[ZERO2:[0-9]+]], v[[ZERO0]]{{$}}
32-
; GCN: v_mov_b32_e32 v[[ZERO3:[0-9]+]], v[[ZERO0]]{{$}}
33-
; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]]
34-
35-
; GCN-DAG: buffer_store_dwordx4 v{{\[}}[[SHIFT]]:[[ZERO3]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
36-
; GCN: s_endpgm
3737
define amdgpu_kernel void @v_uextract_bit_63_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 {
38+
; GCN-LABEL: v_uextract_bit_63_i128:
39+
; GCN: ; %bb.0:
40+
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
41+
; GCN-NEXT: s_mov_b32 s7, 0xf000
42+
; GCN-NEXT: s_mov_b32 s6, 0
43+
; GCN-NEXT: v_lshlrev_b32_e32 v4, 4, v0
44+
; GCN-NEXT: v_mov_b32_e32 v5, 0
45+
; GCN-NEXT: s_waitcnt lgkmcnt(0)
46+
; GCN-NEXT: s_mov_b64 s[8:9], s[2:3]
47+
; GCN-NEXT: s_mov_b64 s[10:11], s[6:7]
48+
; GCN-NEXT: buffer_load_dword v0, v[4:5], s[8:11], 0 addr64 offset:4
49+
; GCN-NEXT: v_mov_b32_e32 v1, v5
50+
; GCN-NEXT: v_mov_b32_e32 v2, v5
51+
; GCN-NEXT: s_mov_b64 s[4:5], s[0:1]
52+
; GCN-NEXT: v_mov_b32_e32 v3, v5
53+
; GCN-NEXT: s_waitcnt vmcnt(0)
54+
; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0
55+
; GCN-NEXT: buffer_store_dwordx4 v[0:3], v[4:5], s[4:7], 0 addr64
56+
; GCN-NEXT: s_endpgm
3857
%id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
3958
%in.gep = getelementptr i128, i128 addrspace(1)* %in, i32 %id.x
4059
%out.gep = getelementptr i128, i128 addrspace(1)* %out, i32 %id.x
@@ -46,17 +65,28 @@ define amdgpu_kernel void @v_uextract_bit_63_i128(i128 addrspace(1)* %out, i128
4665
}
4766

4867
; Extract the high bit of the 3rd quarter
49-
; GCN-LABEL: {{^}}v_uextract_bit_95_i128:
50-
; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
51-
52-
; GCN-DAG: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}}
53-
; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO0]]{{$}}
54-
; GCN: v_mov_b32_e32 v[[ZERO2:[0-9]+]], v[[ZERO0]]{{$}}
55-
; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]]
56-
57-
; GCN-DAG: buffer_store_dwordx4 v{{\[}}[[SHIFT]]:[[ZERO2]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
58-
; GCN: s_endpgm
5968
define amdgpu_kernel void @v_uextract_bit_95_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 {
69+
; GCN-LABEL: v_uextract_bit_95_i128:
70+
; GCN: ; %bb.0:
71+
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
72+
; GCN-NEXT: s_ashr_i32 s3, s2, 31
73+
; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 4
74+
; GCN-NEXT: s_mov_b32 s3, 0xf000
75+
; GCN-NEXT: s_mov_b32 s2, 0
76+
; GCN-NEXT: v_mov_b32_e32 v5, s1
77+
; GCN-NEXT: s_waitcnt lgkmcnt(0)
78+
; GCN-NEXT: s_mov_b64 s[8:9], s[6:7]
79+
; GCN-NEXT: s_mov_b64 s[10:11], s[2:3]
80+
; GCN-NEXT: v_mov_b32_e32 v4, s0
81+
; GCN-NEXT: buffer_load_dword v0, v[4:5], s[8:11], 0 addr64 offset:8
82+
; GCN-NEXT: v_mov_b32_e32 v1, 0
83+
; GCN-NEXT: v_mov_b32_e32 v2, v1
84+
; GCN-NEXT: s_mov_b64 s[0:1], s[4:5]
85+
; GCN-NEXT: v_mov_b32_e32 v3, v1
86+
; GCN-NEXT: s_waitcnt vmcnt(0)
87+
; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0
88+
; GCN-NEXT: buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 addr64
89+
; GCN-NEXT: s_endpgm
6090
%id.x = tail call i32 @llvm.amdgcn.workgroup.id.x()
6191
%in.gep = getelementptr i128, i128 addrspace(1)* %in, i32 %id.x
6292
%out.gep = getelementptr i128, i128 addrspace(1)* %out, i32 %id.x
@@ -68,18 +98,26 @@ define amdgpu_kernel void @v_uextract_bit_95_i128(i128 addrspace(1)* %out, i128
6898
}
6999

70100
; Extract the high bit of the 4th quarter
71-
; GCN-LABEL: {{^}}v_uextract_bit_127_i128:
72-
; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}}
73-
74-
; GCN-DAG: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}}
75-
; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO0]]{{$}}
76-
; GCN: v_mov_b32_e32 v[[ZERO2:[0-9]+]], v[[ZERO0]]{{$}}
77-
; GCN: v_mov_b32_e32 v[[ZERO3:[0-9]+]], v[[ZERO0]]{{$}}
78-
; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]]
79-
80-
; GCN-DAG: buffer_store_dwordx4 v{{\[}}[[SHIFT]]:[[ZERO3]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
81-
; GCN: s_endpgm
82101
define amdgpu_kernel void @v_uextract_bit_127_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 {
102+
; GCN-LABEL: v_uextract_bit_127_i128:
103+
; GCN: ; %bb.0:
104+
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
105+
; GCN-NEXT: s_mov_b32 s7, 0xf000
106+
; GCN-NEXT: s_mov_b32 s6, 0
107+
; GCN-NEXT: v_lshlrev_b32_e32 v4, 4, v0
108+
; GCN-NEXT: v_mov_b32_e32 v5, 0
109+
; GCN-NEXT: s_waitcnt lgkmcnt(0)
110+
; GCN-NEXT: s_mov_b64 s[8:9], s[2:3]
111+
; GCN-NEXT: s_mov_b64 s[10:11], s[6:7]
112+
; GCN-NEXT: buffer_load_dword v0, v[4:5], s[8:11], 0 addr64 offset:12
113+
; GCN-NEXT: v_mov_b32_e32 v1, v5
114+
; GCN-NEXT: v_mov_b32_e32 v2, v5
115+
; GCN-NEXT: s_mov_b64 s[4:5], s[0:1]
116+
; GCN-NEXT: v_mov_b32_e32 v3, v5
117+
; GCN-NEXT: s_waitcnt vmcnt(0)
118+
; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0
119+
; GCN-NEXT: buffer_store_dwordx4 v[0:3], v[4:5], s[4:7], 0 addr64
120+
; GCN-NEXT: s_endpgm
83121
%id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
84122
%in.gep = getelementptr i128, i128 addrspace(1)* %in, i32 %id.x
85123
%out.gep = getelementptr i128, i128 addrspace(1)* %out, i32 %id.x
@@ -91,19 +129,26 @@ define amdgpu_kernel void @v_uextract_bit_127_i128(i128 addrspace(1)* %out, i128
91129
}
92130

93131
; Spans more than 2 dword boundaries
94-
; GCN-LABEL: {{^}}v_uextract_bit_34_100_i128:
95-
; GCN-DAG: buffer_load_dwordx4 v{{\[}}[[VAL0:[0-9]+]]:[[VAL3:[0-9]+]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
96-
97-
; GCN-DAG: v_lshl_b64 v{{\[}}[[SHLLO:[0-9]+]]:[[SHLHI:[0-9]+]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, 30
98-
; GCN-DAG: v_lshrrev_b32_e32 v[[ELT1PART:[0-9]+]], 2, v{{[0-9]+}}
99-
; GCN-DAG: v_bfe_u32 v[[ELT2PART:[0-9]+]], v[[VAL3]], 2, 2{{$}}
100-
; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
101-
; GCN-DAG: v_or_b32_e32 v[[OR0:[0-9]+]], v[[ELT1PART]], v[[SHLLO]]
102-
; GCN-DAG: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO]]{{$}}
103-
104-
; GCN-DAG: buffer_store_dwordx4 v{{\[}}[[OR0]]:[[ZERO1]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
105-
; GCN: s_endpgm
106132
define amdgpu_kernel void @v_uextract_bit_34_100_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 {
133+
; GCN-LABEL: v_uextract_bit_34_100_i128:
134+
; GCN: ; %bb.0:
135+
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
136+
; GCN-NEXT: s_mov_b32 s3, 0xf000
137+
; GCN-NEXT: s_mov_b32 s2, 0
138+
; GCN-NEXT: v_lshlrev_b32_e32 v8, 4, v0
139+
; GCN-NEXT: v_mov_b32_e32 v9, 0
140+
; GCN-NEXT: s_waitcnt lgkmcnt(0)
141+
; GCN-NEXT: s_mov_b64 s[0:1], s[6:7]
142+
; GCN-NEXT: buffer_load_dwordx4 v[0:3], v[8:9], s[0:3], 0 addr64
143+
; GCN-NEXT: s_mov_b64 s[6:7], s[2:3]
144+
; GCN-NEXT: v_mov_b32_e32 v7, v9
145+
; GCN-NEXT: s_waitcnt vmcnt(0)
146+
; GCN-NEXT: v_lshl_b64 v[4:5], v[2:3], 30
147+
; GCN-NEXT: v_lshrrev_b32_e32 v0, 2, v1
148+
; GCN-NEXT: v_bfe_u32 v6, v3, 2, 2
149+
; GCN-NEXT: v_or_b32_e32 v4, v0, v4
150+
; GCN-NEXT: buffer_store_dwordx4 v[4:7], v[8:9], s[4:7], 0 addr64
151+
; GCN-NEXT: s_endpgm
107152
%id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
108153
%in.gep = getelementptr i128, i128 addrspace(1)* %in, i32 %id.x
109154
%out.gep = getelementptr i128, i128 addrspace(1)* %out, i32 %id.x

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