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[RISCV] Add vp.reverse tests for Zvfh and fractional lmuls. NFC
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+412
-45
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4 files changed

+412
-45
lines changed

‎llvm/test/CodeGen/RISCV/rvv/vp-reverse-float-fixed-vectors.ll renamed to ‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-reverser-float.ll

Lines changed: 29 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+v -verify-machineinstrs -riscv-v-vector-bits-min=128 \
2+
; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+v,+zvfh -verify-machineinstrs -riscv-v-vector-bits-min=128 \
33
; RUN: < %s | FileCheck %s
44

55
define <2 x double> @test_vp_reverse_v2f64_masked(<2 x double> %src, <2 x i1> %mask, i32 zeroext %evl) {
@@ -60,5 +60,31 @@ define <4 x float> @test_vp_reverse_v4f32(<4 x float> %src, i32 zeroext %evl) {
6060
ret <4 x float> %dst
6161
}
6262

63-
declare <2 x double> @llvm.experimental.vp.reverse.v2f64(<2 x double>,<2 x i1>,i32)
64-
declare <4 x float> @llvm.experimental.vp.reverse.v4f32(<4 x float>,<4 x i1>,i32)
63+
define <4 x half> @test_vp_reverse_v4f16_masked(<4 x half> %src, <4 x i1> %mask, i32 zeroext %evl) {
64+
; CHECK-LABEL: test_vp_reverse_v4f16_masked:
65+
; CHECK: # %bb.0:
66+
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
67+
; CHECK-NEXT: vid.v v9, v0.t
68+
; CHECK-NEXT: addi a0, a0, -1
69+
; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t
70+
; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t
71+
; CHECK-NEXT: vmv1r.v v8, v9
72+
; CHECK-NEXT: ret
73+
%dst = call <4 x half> @llvm.experimental.vp.reverse.v4f16(<4 x half> %src, <4 x i1> %mask, i32 %evl)
74+
ret <4 x half> %dst
75+
}
76+
77+
define <4 x half> @test_vp_reverse_v4f16(<4 x half> %src, i32 zeroext %evl) {
78+
; CHECK-LABEL: test_vp_reverse_v4f16:
79+
; CHECK: # %bb.0:
80+
; CHECK-NEXT: addi a1, a0, -1
81+
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
82+
; CHECK-NEXT: vid.v v9
83+
; CHECK-NEXT: vrsub.vx v10, v9, a1
84+
; CHECK-NEXT: vrgather.vv v9, v8, v10
85+
; CHECK-NEXT: vmv1r.v v8, v9
86+
; CHECK-NEXT: ret
87+
88+
%dst = call <4 x half> @llvm.experimental.vp.reverse.v4f16(<4 x half> %src, <4 x i1> splat (i1 1), i32 %evl)
89+
ret <4 x half> %dst
90+
}

‎llvm/test/CodeGen/RISCV/rvv/vp-reverse-int-fixed-vectors.ll renamed to ‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-reverser-int.ll

File renamed without changes.

‎llvm/test/CodeGen/RISCV/rvv/vp-reverse-float.ll

Lines changed: 201 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,92 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+v -verify-machineinstrs < %s | FileCheck %s
2+
; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+v,+zvfh -verify-machineinstrs < %s | FileCheck %s
3+
4+
define <vscale x 1 x half> @test_vp_reverse_nxv1f16_masked(<vscale x 1 x half> %src, <vscale x 1 x i1> %mask, i32 zeroext %evl) {
5+
; CHECK-LABEL: test_vp_reverse_nxv1f16_masked:
6+
; CHECK: # %bb.0:
7+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
8+
; CHECK-NEXT: vid.v v9, v0.t
9+
; CHECK-NEXT: addi a0, a0, -1
10+
; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t
11+
; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t
12+
; CHECK-NEXT: vmv1r.v v8, v9
13+
; CHECK-NEXT: ret
14+
%dst = call <vscale x 1 x half> @llvm.experimental.vp.reverse.nxv1f16(<vscale x 1 x half> %src, <vscale x 1 x i1> %mask, i32 %evl)
15+
ret <vscale x 1 x half> %dst
16+
}
17+
18+
define <vscale x 1 x half> @test_vp_reverse_nxv1f16(<vscale x 1 x half> %src, i32 zeroext %evl) {
19+
; CHECK-LABEL: test_vp_reverse_nxv1f16:
20+
; CHECK: # %bb.0:
21+
; CHECK-NEXT: addi a1, a0, -1
22+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
23+
; CHECK-NEXT: vid.v v9
24+
; CHECK-NEXT: vrsub.vx v10, v9, a1
25+
; CHECK-NEXT: vrgather.vv v9, v8, v10
26+
; CHECK-NEXT: vmv1r.v v8, v9
27+
; CHECK-NEXT: ret
28+
29+
%dst = call <vscale x 1 x half> @llvm.experimental.vp.reverse.nxv1f16(<vscale x 1 x half> %src, <vscale x 1 x i1> splat (i1 1), i32 %evl)
30+
ret <vscale x 1 x half> %dst
31+
}
32+
33+
define <vscale x 1 x float> @test_vp_reverse_nxv1f32_masked(<vscale x 1 x float> %src, <vscale x 1 x i1> %mask, i32 zeroext %evl) {
34+
; CHECK-LABEL: test_vp_reverse_nxv1f32_masked:
35+
; CHECK: # %bb.0:
36+
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
37+
; CHECK-NEXT: vid.v v9, v0.t
38+
; CHECK-NEXT: addi a0, a0, -1
39+
; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t
40+
; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t
41+
; CHECK-NEXT: vmv1r.v v8, v9
42+
; CHECK-NEXT: ret
43+
%dst = call <vscale x 1 x float> @llvm.experimental.vp.reverse.nxv1f32(<vscale x 1 x float> %src, <vscale x 1 x i1> %mask, i32 %evl)
44+
ret <vscale x 1 x float> %dst
45+
}
46+
47+
define <vscale x 1 x float> @test_vp_reverse_nxv1f32(<vscale x 1 x float> %src, i32 zeroext %evl) {
48+
; CHECK-LABEL: test_vp_reverse_nxv1f32:
49+
; CHECK: # %bb.0:
50+
; CHECK-NEXT: addi a1, a0, -1
51+
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
52+
; CHECK-NEXT: vid.v v9
53+
; CHECK-NEXT: vrsub.vx v10, v9, a1
54+
; CHECK-NEXT: vrgather.vv v9, v8, v10
55+
; CHECK-NEXT: vmv1r.v v8, v9
56+
; CHECK-NEXT: ret
57+
58+
%dst = call <vscale x 1 x float> @llvm.experimental.vp.reverse.nxv1f32(<vscale x 1 x float> %src, <vscale x 1 x i1> splat (i1 1), i32 %evl)
59+
ret <vscale x 1 x float> %dst
60+
}
61+
62+
define <vscale x 2 x half> @test_vp_reverse_nxv2f16_masked(<vscale x 2 x half> %src, <vscale x 2 x i1> %mask, i32 zeroext %evl) {
63+
; CHECK-LABEL: test_vp_reverse_nxv2f16_masked:
64+
; CHECK: # %bb.0:
65+
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
66+
; CHECK-NEXT: vid.v v9, v0.t
67+
; CHECK-NEXT: addi a0, a0, -1
68+
; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t
69+
; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t
70+
; CHECK-NEXT: vmv1r.v v8, v9
71+
; CHECK-NEXT: ret
72+
%dst = call <vscale x 2 x half> @llvm.experimental.vp.reverse.nxv2f16(<vscale x 2 x half> %src, <vscale x 2 x i1> %mask, i32 %evl)
73+
ret <vscale x 2 x half> %dst
74+
}
75+
76+
define <vscale x 2 x half> @test_vp_reverse_nxv2f16(<vscale x 2 x half> %src, i32 zeroext %evl) {
77+
; CHECK-LABEL: test_vp_reverse_nxv2f16:
78+
; CHECK: # %bb.0:
79+
; CHECK-NEXT: addi a1, a0, -1
80+
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
81+
; CHECK-NEXT: vid.v v9
82+
; CHECK-NEXT: vrsub.vx v10, v9, a1
83+
; CHECK-NEXT: vrgather.vv v9, v8, v10
84+
; CHECK-NEXT: vmv1r.v v8, v9
85+
; CHECK-NEXT: ret
86+
87+
%dst = call <vscale x 2 x half> @llvm.experimental.vp.reverse.nxv2f16(<vscale x 2 x half> %src, <vscale x 2 x i1> splat (i1 1), i32 %evl)
88+
ret <vscale x 2 x half> %dst
89+
}
390

491
define <vscale x 1 x double> @test_vp_reverse_nxv1f64_masked(<vscale x 1 x double> %src, <vscale x 1 x i1> %mask, i32 zeroext %evl) {
592
; CHECK-LABEL: test_vp_reverse_nxv1f64_masked:
@@ -59,6 +146,35 @@ define <vscale x 2 x float> @test_vp_reverse_nxv2f32(<vscale x 2 x float> %src,
59146
ret <vscale x 2 x float> %dst
60147
}
61148

149+
define <vscale x 4 x half> @test_vp_reverse_nxv4f16_masked(<vscale x 4 x half> %src, <vscale x 4 x i1> %mask, i32 zeroext %evl) {
150+
; CHECK-LABEL: test_vp_reverse_nxv4f16_masked:
151+
; CHECK: # %bb.0:
152+
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
153+
; CHECK-NEXT: vid.v v9, v0.t
154+
; CHECK-NEXT: addi a0, a0, -1
155+
; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t
156+
; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t
157+
; CHECK-NEXT: vmv.v.v v8, v9
158+
; CHECK-NEXT: ret
159+
%dst = call <vscale x 4 x half> @llvm.experimental.vp.reverse.nxv4f16(<vscale x 4 x half> %src, <vscale x 4 x i1> %mask, i32 %evl)
160+
ret <vscale x 4 x half> %dst
161+
}
162+
163+
define <vscale x 4 x half> @test_vp_reverse_nxv4f16(<vscale x 4 x half> %src, i32 zeroext %evl) {
164+
; CHECK-LABEL: test_vp_reverse_nxv4f16:
165+
; CHECK: # %bb.0:
166+
; CHECK-NEXT: addi a1, a0, -1
167+
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
168+
; CHECK-NEXT: vid.v v9
169+
; CHECK-NEXT: vrsub.vx v10, v9, a1
170+
; CHECK-NEXT: vrgather.vv v9, v8, v10
171+
; CHECK-NEXT: vmv.v.v v8, v9
172+
; CHECK-NEXT: ret
173+
174+
%dst = call <vscale x 4 x half> @llvm.experimental.vp.reverse.nxv4f16(<vscale x 4 x half> %src, <vscale x 4 x i1> splat (i1 1), i32 %evl)
175+
ret <vscale x 4 x half> %dst
176+
}
177+
62178
define <vscale x 2 x double> @test_vp_reverse_nxv2f64_masked(<vscale x 2 x double> %src, <vscale x 2 x i1> %mask, i32 zeroext %evl) {
63179
; CHECK-LABEL: test_vp_reverse_nxv2f64_masked:
64180
; CHECK: # %bb.0:
@@ -117,6 +233,35 @@ define <vscale x 4 x float> @test_vp_reverse_nxv4f32(<vscale x 4 x float> %src,
117233
ret <vscale x 4 x float> %dst
118234
}
119235

236+
define <vscale x 8 x half> @test_vp_reverse_nxv8f16_masked(<vscale x 8 x half> %src, <vscale x 8 x i1> %mask, i32 zeroext %evl) {
237+
; CHECK-LABEL: test_vp_reverse_nxv8f16_masked:
238+
; CHECK: # %bb.0:
239+
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
240+
; CHECK-NEXT: vid.v v10, v0.t
241+
; CHECK-NEXT: addi a0, a0, -1
242+
; CHECK-NEXT: vrsub.vx v12, v10, a0, v0.t
243+
; CHECK-NEXT: vrgather.vv v10, v8, v12, v0.t
244+
; CHECK-NEXT: vmv.v.v v8, v10
245+
; CHECK-NEXT: ret
246+
%dst = call <vscale x 8 x half> @llvm.experimental.vp.reverse.nxv8f16(<vscale x 8 x half> %src, <vscale x 8 x i1> %mask, i32 %evl)
247+
ret <vscale x 8 x half> %dst
248+
}
249+
250+
define <vscale x 8 x half> @test_vp_reverse_nxv8f16(<vscale x 8 x half> %src, i32 zeroext %evl) {
251+
; CHECK-LABEL: test_vp_reverse_nxv8f16:
252+
; CHECK: # %bb.0:
253+
; CHECK-NEXT: addi a1, a0, -1
254+
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
255+
; CHECK-NEXT: vid.v v10
256+
; CHECK-NEXT: vrsub.vx v12, v10, a1
257+
; CHECK-NEXT: vrgather.vv v10, v8, v12
258+
; CHECK-NEXT: vmv.v.v v8, v10
259+
; CHECK-NEXT: ret
260+
261+
%dst = call <vscale x 8 x half> @llvm.experimental.vp.reverse.nxv8f16(<vscale x 8 x half> %src, <vscale x 8 x i1> splat (i1 1), i32 %evl)
262+
ret <vscale x 8 x half> %dst
263+
}
264+
120265
define <vscale x 4 x double> @test_vp_reverse_nxv4f64_masked(<vscale x 4 x double> %src, <vscale x 4 x i1> %mask, i32 zeroext %evl) {
121266
; CHECK-LABEL: test_vp_reverse_nxv4f64_masked:
122267
; CHECK: # %bb.0:
@@ -175,6 +320,35 @@ define <vscale x 8 x float> @test_vp_reverse_nxv8f32(<vscale x 8 x float> %src,
175320
ret <vscale x 8 x float> %dst
176321
}
177322

323+
define <vscale x 16 x half> @test_vp_reverse_nxv16f16_masked(<vscale x 16 x half> %src, <vscale x 16 x i1> %mask, i32 zeroext %evl) {
324+
; CHECK-LABEL: test_vp_reverse_nxv16f16_masked:
325+
; CHECK: # %bb.0:
326+
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
327+
; CHECK-NEXT: vid.v v12, v0.t
328+
; CHECK-NEXT: addi a0, a0, -1
329+
; CHECK-NEXT: vrsub.vx v16, v12, a0, v0.t
330+
; CHECK-NEXT: vrgather.vv v12, v8, v16, v0.t
331+
; CHECK-NEXT: vmv.v.v v8, v12
332+
; CHECK-NEXT: ret
333+
%dst = call <vscale x 16 x half> @llvm.experimental.vp.reverse.nxv16f16(<vscale x 16 x half> %src, <vscale x 16 x i1> %mask, i32 %evl)
334+
ret <vscale x 16 x half> %dst
335+
}
336+
337+
define <vscale x 16 x half> @test_vp_reverse_nxv16f16(<vscale x 16 x half> %src, i32 zeroext %evl) {
338+
; CHECK-LABEL: test_vp_reverse_nxv16f16:
339+
; CHECK: # %bb.0:
340+
; CHECK-NEXT: addi a1, a0, -1
341+
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
342+
; CHECK-NEXT: vid.v v12
343+
; CHECK-NEXT: vrsub.vx v16, v12, a1
344+
; CHECK-NEXT: vrgather.vv v12, v8, v16
345+
; CHECK-NEXT: vmv.v.v v8, v12
346+
; CHECK-NEXT: ret
347+
348+
%dst = call <vscale x 16 x half> @llvm.experimental.vp.reverse.nxv16f16(<vscale x 16 x half> %src, <vscale x 16 x i1> splat (i1 1), i32 %evl)
349+
ret <vscale x 16 x half> %dst
350+
}
351+
178352
define <vscale x 8 x double> @test_vp_reverse_nxv8f64_masked(<vscale x 8 x double> %src, <vscale x 8 x i1> %mask, i32 zeroext %evl) {
179353
; CHECK-LABEL: test_vp_reverse_nxv8f64_masked:
180354
; CHECK: # %bb.0:
@@ -233,18 +407,31 @@ define <vscale x 16 x float> @test_vp_reverse_nxv16f32(<vscale x 16 x float> %sr
233407
ret <vscale x 16 x float> %dst
234408
}
235409

236-
; LMUL = 1
237-
declare <vscale x 1 x double> @llvm.experimental.vp.reverse.nxv1f64(<vscale x 1 x double>,<vscale x 1 x i1>,i32)
238-
declare <vscale x 2 x float> @llvm.experimental.vp.reverse.nxv2f32(<vscale x 2 x float>,<vscale x 2 x i1>,i32)
239-
240-
; LMUL = 2
241-
declare <vscale x 2 x double> @llvm.experimental.vp.reverse.nxv2f64(<vscale x 2 x double>,<vscale x 2 x i1>,i32)
242-
declare <vscale x 4 x float> @llvm.experimental.vp.reverse.nxv4f32(<vscale x 4 x float>,<vscale x 4 x i1>,i32)
410+
define <vscale x 32 x half> @test_vp_reverse_nxv32f16_masked(<vscale x 32 x half> %src, <vscale x 32 x i1> %mask, i32 zeroext %evl) {
411+
; CHECK-LABEL: test_vp_reverse_nxv32f16_masked:
412+
; CHECK: # %bb.0:
413+
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
414+
; CHECK-NEXT: vid.v v16, v0.t
415+
; CHECK-NEXT: addi a0, a0, -1
416+
; CHECK-NEXT: vrsub.vx v24, v16, a0, v0.t
417+
; CHECK-NEXT: vrgather.vv v16, v8, v24, v0.t
418+
; CHECK-NEXT: vmv.v.v v8, v16
419+
; CHECK-NEXT: ret
420+
%dst = call <vscale x 32 x half> @llvm.experimental.vp.reverse.nxv32f16(<vscale x 32 x half> %src, <vscale x 32 x i1> %mask, i32 %evl)
421+
ret <vscale x 32 x half> %dst
422+
}
243423

244-
; LMUL = 4
245-
declare <vscale x 4 x double> @llvm.experimental.vp.reverse.nxv4f64(<vscale x 4 x double>,<vscale x 4 x i1>,i32)
246-
declare <vscale x 8 x float> @llvm.experimental.vp.reverse.nxv8f32(<vscale x 8 x float>,<vscale x 8 x i1>,i32)
424+
define <vscale x 32 x half> @test_vp_reverse_nxv32f16(<vscale x 32 x half> %src, i32 zeroext %evl) {
425+
; CHECK-LABEL: test_vp_reverse_nxv32f16:
426+
; CHECK: # %bb.0:
427+
; CHECK-NEXT: addi a1, a0, -1
428+
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
429+
; CHECK-NEXT: vid.v v16
430+
; CHECK-NEXT: vrsub.vx v24, v16, a1
431+
; CHECK-NEXT: vrgather.vv v16, v8, v24
432+
; CHECK-NEXT: vmv.v.v v8, v16
433+
; CHECK-NEXT: ret
247434

248-
; LMUL = 8
249-
declare <vscale x 8 x double> @llvm.experimental.vp.reverse.nxv8f64(<vscale x 8 x double>,<vscale x 8 x i1>,i32)
250-
declare <vscale x 16 x float> @llvm.experimental.vp.reverse.nxv16f32(<vscale x 16 x float>,<vscale x 16 x i1>,i32)
435+
%dst = call <vscale x 32 x half> @llvm.experimental.vp.reverse.nxv32f16(<vscale x 32 x half> %src, <vscale x 32 x i1> splat (i1 1), i32 %evl)
436+
ret <vscale x 32 x half> %dst
437+
}

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