@@ -452,16 +452,16 @@ multiclass VPseudoVCPOP {
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}
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}
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- multiclass VPseudoVWALU_VV_VX_VI<Operand ImmType> {
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+ multiclass VPseudoVWSLL {
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foreach m = MxListW in {
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defvar mx = m.MX;
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defm "" : VPseudoBinaryW_VV<m>,
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SchedBinary<"WriteVWSLLV", "ReadVWSLLV", "ReadVWSLLV", mx,
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forceMergeOpRead=true>;
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- defm "" : VPseudoBinaryW_VX<m>,
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+ defm "" : VPseudoBinaryW_VX<m>,
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SchedBinary<"WriteVWSLLX", "ReadVWSLLV", "ReadVWSLLX", mx,
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forceMergeOpRead=true>;
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- defm "" : VPseudoBinaryW_VI<ImmType , m>,
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+ defm "" : VPseudoBinaryW_VI<uimm5 , m>,
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SchedUnary<"WriteVWSLLI", "ReadVWSLLV", mx,
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forceMergeOpRead=true>;
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}
@@ -525,7 +525,7 @@ let Predicates = [HasStdExtZvbb] in {
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defm PseudoVCLZ : VPseudoVCLZ;
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defm PseudoVCTZ : VPseudoVCTZ;
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defm PseudoVCPOP : VPseudoVCPOP;
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- defm PseudoVWSLL : VPseudoVWALU_VV_VX_VI<uimm5> ;
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+ defm PseudoVWSLL : VPseudoVWSLL ;
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} // Predicates = [HasStdExtZvbb]
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let Predicates = [HasStdExtZvbc] in {
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