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[RISCV] Add IsSignExtendingOpW to amocas.w. (#79351)
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+3
-4
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llvm/lib/Target/RISCV/RISCVInstrInfoZa.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ multiclass AMO_cas_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr,
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def _AQ_RL : AMO_cas<funct5, 1, 1, funct3, opcodestr # ".aqrl", RC>;
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}
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let Predicates = [HasStdExtZacas] in {
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let Predicates = [HasStdExtZacas], IsSignExtendingOpW = 1 in {
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defm AMOCAS_W : AMO_cas_aq_rl<0b00101, 0b010, "amocas.w", GPR>;
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} // Predicates = [HasStdExtZacas]
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llvm/test/CodeGen/RISCV/atomic-signext.ll

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5525,11 +5525,10 @@ define signext i32 @cmpxchg_i32_monotonic_crossbb(ptr %ptr, i32 signext %cmp, i3
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; RV64IA-ZACAS-NEXT: beqz a3, .LBB64_2
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; RV64IA-ZACAS-NEXT: # %bb.1: # %then
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; RV64IA-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0)
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; RV64IA-ZACAS-NEXT: sext.w a0, a1
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; RV64IA-ZACAS-NEXT: mv a0, a1
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; RV64IA-ZACAS-NEXT: ret
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; RV64IA-ZACAS-NEXT: .LBB64_2: # %else
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; RV64IA-ZACAS-NEXT: lw a1, 0(a0)
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; RV64IA-ZACAS-NEXT: sext.w a0, a1
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; RV64IA-ZACAS-NEXT: lw a0, 0(a0)
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; RV64IA-ZACAS-NEXT: ret
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br i1 %c, label %then, label %else
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