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AMDGPU: Expand raw ptr buffer atomic fadd tests
These were only checking the no return versions on gfx908
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‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll

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‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx908 < %s | FileCheck -check-prefix=GFX908 %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx90a < %s | FileCheck -check-prefix=GFX90A %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx940 < %s | FileCheck -check-prefix=GFX940 %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s
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define void @raw_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(float %val, ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) #0 {
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; GFX908-LABEL: raw_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
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; GFX908: ; %bb.0:
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; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX908-NEXT: buffer_atomic_add_f32 v0, v1, s[4:7], s8 offen
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; GFX908-NEXT: s_waitcnt vmcnt(0)
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; GFX908-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX90A-LABEL: raw_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
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; GFX90A: ; %bb.0:
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; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX90A-NEXT: buffer_atomic_add_f32 v0, v1, s[4:7], s8 offen scc
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; GFX90A-NEXT: s_waitcnt vmcnt(0)
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; GFX90A-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX940-LABEL: raw_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
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; GFX940: ; %bb.0:
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; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX940-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], s4 offen sc1
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; GFX940-NEXT: s_waitcnt vmcnt(0)
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; GFX940-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: raw_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], s4 offen scope:SCOPE_SYS
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%ret = call float @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 24)
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ret void
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}
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define void @raw_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(float %val, ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) #0 {
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; GFX908-LABEL: raw_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
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; GFX908: ; %bb.0:
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; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX908-NEXT: buffer_atomic_add_f32 v0, off, s[4:7], s8
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; GFX908-NEXT: s_waitcnt vmcnt(0)
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; GFX908-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX90A-LABEL: raw_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
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; GFX90A: ; %bb.0:
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; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX90A-NEXT: buffer_atomic_add_f32 v0, off, s[4:7], s8
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; GFX90A-NEXT: s_waitcnt vmcnt(0)
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; GFX90A-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX940-LABEL: raw_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
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; GFX940: ; %bb.0:
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; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX940-NEXT: buffer_atomic_add_f32 v0, off, s[0:3], s4
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; GFX940-NEXT: s_waitcnt vmcnt(0)
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; GFX940-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: raw_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: buffer_atomic_add_f32 v0, off, s[0:3], s4
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%ret = call float @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f32(float %val, ptr addrspace(8) %rsrc, i32 0, i32 %soffset, i32 0)
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ret void
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}
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define void @raw_ptr_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<2 x half> %val, ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) #0 {
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; GFX908-LABEL: raw_ptr_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
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; GFX908: ; %bb.0:
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; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX908-NEXT: buffer_atomic_pk_add_f16 v0, v1, s[4:7], s8 offen
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; GFX908-NEXT: s_waitcnt vmcnt(0)
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; GFX908-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX90A-LABEL: raw_ptr_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
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; GFX90A: ; %bb.0:
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; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX90A-NEXT: buffer_atomic_pk_add_f16 v0, v1, s[4:7], s8 offen
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; GFX90A-NEXT: s_waitcnt vmcnt(0)
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; GFX90A-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX940-LABEL: raw_ptr_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
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; GFX940: ; %bb.0:
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; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX940-NEXT: buffer_atomic_pk_add_f16 v0, v1, s[0:3], s4 offen
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; GFX940-NEXT: s_waitcnt vmcnt(0)
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; GFX940-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: raw_ptr_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: buffer_atomic_pk_add_f16 v0, v1, s[0:3], s4 offen
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%ret = call <2 x half> @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2f16(<2 x half> %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 0)
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ret void
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}
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define void @raw_ptr_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(<2 x half> %val, ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) #0 {
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; GFX908-LABEL: raw_ptr_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
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; GFX908: ; %bb.0:
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; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX908-NEXT: buffer_atomic_pk_add_f16 v0, off, s[4:7], s8 offset:92
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; GFX908-NEXT: s_waitcnt vmcnt(0)
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; GFX908-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX90A-LABEL: raw_ptr_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
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; GFX90A: ; %bb.0:
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; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX90A-NEXT: buffer_atomic_pk_add_f16 v0, off, s[4:7], s8 offset:92
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; GFX90A-NEXT: s_waitcnt vmcnt(0)
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; GFX90A-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX940-LABEL: raw_ptr_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
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; GFX940: ; %bb.0:
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; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX940-NEXT: buffer_atomic_pk_add_f16 v0, off, s[0:3], s4 offset:92
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; GFX940-NEXT: s_waitcnt vmcnt(0)
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; GFX940-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: raw_ptr_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: buffer_atomic_pk_add_f16 v0, off, s[0:3], s4 offset:92
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%ret = call <2 x half> @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2f16(<2 x half> %val, ptr addrspace(8) %rsrc, i32 92, i32 %soffset, i32 0)
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ret void
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}
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define void @raw_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(float %val, ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) #0 {
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; GFX908-LABEL: raw_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:
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; GFX908: ; %bb.0:
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; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX908-NEXT: buffer_atomic_add_f32 v0, v1, s[4:7], s8 offen slc
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; GFX908-NEXT: s_waitcnt vmcnt(0)
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; GFX908-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX90A-LABEL: raw_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:
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; GFX90A: ; %bb.0:
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; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX90A-NEXT: buffer_atomic_add_f32 v0, v1, s[4:7], s8 offen slc
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; GFX90A-NEXT: s_waitcnt vmcnt(0)
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; GFX90A-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX940-LABEL: raw_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:
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; GFX940: ; %bb.0:
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; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX940-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], s4 offen nt
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; GFX940-NEXT: s_waitcnt vmcnt(0)
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; GFX940-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: raw_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], s4 offen th:TH_ATOMIC_NT
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%ret = call float @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 2)
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ret void
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}
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declare float @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f32(float, ptr addrspace(8), i32, i32, i32 immarg)
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declare <2 x half> @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2f16(<2 x half>, ptr addrspace(8), i32, i32, i32 immarg)
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attributes #0 = { nounwind }

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