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[RISCV] Split RISCVDisassembler::getInstruction into a 16-bit and 32-bit version. (#90254)
This reduces nesting of the common 32-bit case and makes it easier to add longer instruction lengths in the future.
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‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

Lines changed: 119 additions & 99 deletions
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,13 @@ class RISCVDisassembler : public MCDisassembler {
4444

4545
private:
4646
void addSPOperands(MCInst &MI) const;
47+
48+
DecodeStatus getInstruction32(MCInst &Instr, uint64_t &Size,
49+
ArrayRef<uint8_t> Bytes, uint64_t Address,
50+
raw_ostream &CStream) const;
51+
DecodeStatus getInstruction16(MCInst &Instr, uint64_t &Size,
52+
ArrayRef<uint8_t> Bytes, uint64_t Address,
53+
raw_ostream &CStream) const;
4754
};
4855
} // end anonymous namespace
4956

@@ -502,21 +509,13 @@ void RISCVDisassembler::addSPOperands(MCInst &MI) const {
502509
MI.insert(MI.begin() + i, MCOperand::createReg(RISCV::X2));
503510
}
504511

505-
DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
506-
ArrayRef<uint8_t> Bytes,
507-
uint64_t Address,
508-
raw_ostream &CS) const {
509-
// TODO: This will need modification when supporting instruction set
510-
// extensions with instructions > 32-bits (up to 176 bits wide).
511-
uint32_t Insn;
512-
DecodeStatus Result;
513-
514512
#define TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION(FEATURE_CHECKS, DECODER_TABLE, \
515513
DESC, ADDITIONAL_OPERATION) \
516514
do { \
517515
if (FEATURE_CHECKS) { \
518516
LLVM_DEBUG(dbgs() << "Trying " DESC ":\n"); \
519-
Result = decodeInstruction(DECODER_TABLE, MI, Insn, Address, this, STI); \
517+
DecodeStatus Result = \
518+
decodeInstruction(DECODER_TABLE, MI, Insn, Address, this, STI); \
520519
if (Result != MCDisassembler::Fail) { \
521520
ADDITIONAL_OPERATION; \
522521
return Result; \
@@ -532,104 +531,111 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
532531
#define TRY_TO_DECODE_FEATURE(FEATURE, DECODER_TABLE, DESC) \
533532
TRY_TO_DECODE(STI.hasFeature(FEATURE), DECODER_TABLE, DESC)
534533

535-
// It's a 32 bit instruction if bit 0 and 1 are 1.
536-
if ((Bytes[0] & 0x3) == 0x3) {
537-
if (Bytes.size() < 4) {
538-
Size = 0;
539-
return MCDisassembler::Fail;
540-
}
541-
Size = 4;
542-
543-
Insn = support::endian::read32le(Bytes.data());
544-
545-
TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZdinx) &&
546-
!STI.hasFeature(RISCV::Feature64Bit),
547-
DecoderTableRV32Zdinx32,
548-
"RV32Zdinx table (Double in Integer and rv32)");
549-
TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZacas) &&
550-
!STI.hasFeature(RISCV::Feature64Bit),
551-
DecoderTableRV32Zacas32,
552-
"RV32Zacas table (Compare-And-Swap and rv32)");
553-
TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZfinx, DecoderTableRVZfinx32,
554-
"RVZfinx table (Float in Integer)");
555-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXVentanaCondOps,
556-
DecoderTableXVentana32, "Ventana custom opcode table");
557-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBa, DecoderTableXTHeadBa32,
558-
"XTHeadBa custom opcode table");
559-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBb, DecoderTableXTHeadBb32,
560-
"XTHeadBb custom opcode table");
561-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBs, DecoderTableXTHeadBs32,
562-
"XTHeadBs custom opcode table");
563-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCondMov,
564-
DecoderTableXTHeadCondMov32,
565-
"XTHeadCondMov custom opcode table");
566-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCmo, DecoderTableXTHeadCmo32,
567-
"XTHeadCmo custom opcode table");
568-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadFMemIdx,
569-
DecoderTableXTHeadFMemIdx32,
570-
"XTHeadFMemIdx custom opcode table");
571-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMac, DecoderTableXTHeadMac32,
572-
"XTHeadMac custom opcode table");
573-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemIdx,
574-
DecoderTableXTHeadMemIdx32,
575-
"XTHeadMemIdx custom opcode table");
576-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemPair,
577-
DecoderTableXTHeadMemPair32,
578-
"XTHeadMemPair custom opcode table");
579-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadSync,
580-
DecoderTableXTHeadSync32,
581-
"XTHeadSync custom opcode table");
582-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadVdot, DecoderTableXTHeadVdot32,
583-
"XTHeadVdot custom opcode table");
584-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
585-
"SiFive VCIX custom opcode table");
586-
TRY_TO_DECODE_FEATURE(
587-
RISCV::FeatureVendorXSfvqmaccdod, DecoderTableXSfvqmaccdod32,
588-
"SiFive Matrix Multiplication (2x8 and 8x2) Instruction opcode table");
589-
TRY_TO_DECODE_FEATURE(
590-
RISCV::FeatureVendorXSfvqmaccqoq, DecoderTableXSfvqmaccqoq32,
591-
"SiFive Matrix Multiplication (4x8 and 8x4) Instruction opcode table");
592-
TRY_TO_DECODE_FEATURE(
593-
RISCV::FeatureVendorXSfvfwmaccqqq, DecoderTableXSfvfwmaccqqq32,
594-
"SiFive Matrix Multiplication Instruction opcode table");
595-
TRY_TO_DECODE_FEATURE(
596-
RISCV::FeatureVendorXSfvfnrclipxfqf, DecoderTableXSfvfnrclipxfqf32,
597-
"SiFive FP32-to-int8 Ranged Clip Instructions opcode table");
598-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecdiscarddlone,
599-
DecoderTableXSiFivecdiscarddlone32,
600-
"SiFive sf.cdiscard.d.l1 custom opcode table");
601-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecflushdlone,
602-
DecoderTableXSiFivecflushdlone32,
603-
"SiFive sf.cflush.d.l1 custom opcode table");
604-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcease, DecoderTableXSfcease32,
605-
"SiFive sf.cease custom opcode table");
606-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
607-
DecoderTableXCVbitmanip32,
608-
"CORE-V Bit Manipulation custom opcode table");
609-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVelw, DecoderTableXCVelw32,
610-
"CORE-V Event load custom opcode table");
611-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32,
612-
"CORE-V MAC custom opcode table");
613-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmem, DecoderTableXCVmem32,
614-
"CORE-V MEM custom opcode table");
615-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCValu, DecoderTableXCValu32,
616-
"CORE-V ALU custom opcode table");
617-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVsimd, DecoderTableXCVsimd32,
618-
"CORE-V SIMD extensions custom opcode table");
619-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32,
620-
"CORE-V Immediate Branching custom opcode table");
621-
TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
622-
534+
DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
535+
ArrayRef<uint8_t> Bytes,
536+
uint64_t Address,
537+
raw_ostream &CS) const {
538+
if (Bytes.size() < 4) {
539+
Size = 0;
623540
return MCDisassembler::Fail;
624541
}
542+
Size = 4;
543+
544+
uint32_t Insn = support::endian::read32le(Bytes.data());
545+
546+
TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZdinx) &&
547+
!STI.hasFeature(RISCV::Feature64Bit),
548+
DecoderTableRV32Zdinx32,
549+
"RV32Zdinx table (Double in Integer and rv32)");
550+
TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZacas) &&
551+
!STI.hasFeature(RISCV::Feature64Bit),
552+
DecoderTableRV32Zacas32,
553+
"RV32Zacas table (Compare-And-Swap and rv32)");
554+
TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZfinx, DecoderTableRVZfinx32,
555+
"RVZfinx table (Float in Integer)");
556+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXVentanaCondOps,
557+
DecoderTableXVentana32, "Ventana custom opcode table");
558+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBa, DecoderTableXTHeadBa32,
559+
"XTHeadBa custom opcode table");
560+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBb, DecoderTableXTHeadBb32,
561+
"XTHeadBb custom opcode table");
562+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBs, DecoderTableXTHeadBs32,
563+
"XTHeadBs custom opcode table");
564+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCondMov,
565+
DecoderTableXTHeadCondMov32,
566+
"XTHeadCondMov custom opcode table");
567+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCmo, DecoderTableXTHeadCmo32,
568+
"XTHeadCmo custom opcode table");
569+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadFMemIdx,
570+
DecoderTableXTHeadFMemIdx32,
571+
"XTHeadFMemIdx custom opcode table");
572+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMac, DecoderTableXTHeadMac32,
573+
"XTHeadMac custom opcode table");
574+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemIdx,
575+
DecoderTableXTHeadMemIdx32,
576+
"XTHeadMemIdx custom opcode table");
577+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemPair,
578+
DecoderTableXTHeadMemPair32,
579+
"XTHeadMemPair custom opcode table");
580+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadSync,
581+
DecoderTableXTHeadSync32,
582+
"XTHeadSync custom opcode table");
583+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadVdot,
584+
DecoderTableXTHeadVdot32,
585+
"XTHeadVdot custom opcode table");
586+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
587+
"SiFive VCIX custom opcode table");
588+
TRY_TO_DECODE_FEATURE(
589+
RISCV::FeatureVendorXSfvqmaccdod, DecoderTableXSfvqmaccdod32,
590+
"SiFive Matrix Multiplication (2x8 and 8x2) Instruction opcode table");
591+
TRY_TO_DECODE_FEATURE(
592+
RISCV::FeatureVendorXSfvqmaccqoq, DecoderTableXSfvqmaccqoq32,
593+
"SiFive Matrix Multiplication (4x8 and 8x4) Instruction opcode table");
594+
TRY_TO_DECODE_FEATURE(
595+
RISCV::FeatureVendorXSfvfwmaccqqq, DecoderTableXSfvfwmaccqqq32,
596+
"SiFive Matrix Multiplication Instruction opcode table");
597+
TRY_TO_DECODE_FEATURE(
598+
RISCV::FeatureVendorXSfvfnrclipxfqf, DecoderTableXSfvfnrclipxfqf32,
599+
"SiFive FP32-to-int8 Ranged Clip Instructions opcode table");
600+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecdiscarddlone,
601+
DecoderTableXSiFivecdiscarddlone32,
602+
"SiFive sf.cdiscard.d.l1 custom opcode table");
603+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecflushdlone,
604+
DecoderTableXSiFivecflushdlone32,
605+
"SiFive sf.cflush.d.l1 custom opcode table");
606+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcease, DecoderTableXSfcease32,
607+
"SiFive sf.cease custom opcode table");
608+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
609+
DecoderTableXCVbitmanip32,
610+
"CORE-V Bit Manipulation custom opcode table");
611+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVelw, DecoderTableXCVelw32,
612+
"CORE-V Event load custom opcode table");
613+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32,
614+
"CORE-V MAC custom opcode table");
615+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmem, DecoderTableXCVmem32,
616+
"CORE-V MEM custom opcode table");
617+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCValu, DecoderTableXCValu32,
618+
"CORE-V ALU custom opcode table");
619+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVsimd, DecoderTableXCVsimd32,
620+
"CORE-V SIMD extensions custom opcode table");
621+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32,
622+
"CORE-V Immediate Branching custom opcode table");
623+
TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
625624

625+
return MCDisassembler::Fail;
626+
}
627+
628+
DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size,
629+
ArrayRef<uint8_t> Bytes,
630+
uint64_t Address,
631+
raw_ostream &CS) const {
626632
if (Bytes.size() < 2) {
627633
Size = 0;
628634
return MCDisassembler::Fail;
629635
}
630636
Size = 2;
631637

632-
Insn = support::endian::read16le(Bytes.data());
638+
uint32_t Insn = support::endian::read16le(Bytes.data());
633639
TRY_TO_DECODE_AND_ADD_SP(!STI.hasFeature(RISCV::Feature64Bit),
634640
DecoderTableRISCV32Only_16,
635641
"RISCV32Only_16 table (16-bit Instruction)");
@@ -645,3 +651,17 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
645651

646652
return MCDisassembler::Fail;
647653
}
654+
655+
DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
656+
ArrayRef<uint8_t> Bytes,
657+
uint64_t Address,
658+
raw_ostream &CS) const {
659+
// TODO: This will need modification when supporting instruction set
660+
// extensions with instructions > 32-bits (up to 176 bits wide).
661+
662+
// It's a 32 bit instruction if bit 0 and 1 are 1.
663+
if ((Bytes[0] & 0x3) == 0x3)
664+
return getInstruction32(MI, Size, Bytes, Address, CS);
665+
666+
return getInstruction16(MI, Size, Bytes, Address, CS);
667+
}

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