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[LoongArch][NFC] Pre-commit tests for LSX/LASX bswap codegen (#114170)
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‎llvm/test/CodeGen/LoongArch/lasx/bswap.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
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define void @bswap_v16i16(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: bswap_v16i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: xvsrli.h $xr1, $xr0, 8
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; CHECK-NEXT: xvslli.h $xr0, $xr0, 8
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a1, 0
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; CHECK-NEXT: ret
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%v = load <16 x i16>, ptr %src
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%res = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %v)
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store <16 x i16> %res, ptr %dst
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ret void
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}
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define void @bswap_v8i32(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: bswap_v8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: lu12i.w $a0, 15
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; CHECK-NEXT: ori $a0, $a0, 3840
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; CHECK-NEXT: xvreplgr2vr.w $xr1, $a0
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; CHECK-NEXT: xvsrli.w $xr2, $xr0, 8
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; CHECK-NEXT: xvand.v $xr2, $xr2, $xr1
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; CHECK-NEXT: xvsrli.w $xr3, $xr0, 24
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; CHECK-NEXT: xvor.v $xr2, $xr2, $xr3
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; CHECK-NEXT: xvand.v $xr1, $xr0, $xr1
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; CHECK-NEXT: xvslli.w $xr1, $xr1, 8
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; CHECK-NEXT: xvslli.w $xr0, $xr0, 24
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr2
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; CHECK-NEXT: xvst $xr0, $a1, 0
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; CHECK-NEXT: ret
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%v = load <8 x i32>, ptr %src
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%res = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %v)
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store <8 x i32> %res, ptr %dst
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ret void
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}
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define void @bswap_v4i64(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: bswap_v4i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: lu12i.w $a0, 4080
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; CHECK-NEXT: xvreplgr2vr.d $xr1, $a0
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; CHECK-NEXT: xvsrli.d $xr2, $xr0, 24
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; CHECK-NEXT: xvand.v $xr2, $xr2, $xr1
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; CHECK-NEXT: lu12i.w $a0, -4096
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; CHECK-NEXT: lu32i.d $a0, 0
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; CHECK-NEXT: xvreplgr2vr.d $xr3, $a0
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; CHECK-NEXT: xvsrli.d $xr4, $xr0, 8
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; CHECK-NEXT: xvand.v $xr4, $xr4, $xr3
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; CHECK-NEXT: xvor.v $xr2, $xr4, $xr2
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; CHECK-NEXT: lu12i.w $a0, 15
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; CHECK-NEXT: ori $a0, $a0, 3840
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; CHECK-NEXT: xvreplgr2vr.d $xr4, $a0
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; CHECK-NEXT: xvsrli.d $xr5, $xr0, 40
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; CHECK-NEXT: xvand.v $xr5, $xr5, $xr4
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; CHECK-NEXT: xvsrli.d $xr6, $xr0, 56
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; CHECK-NEXT: xvor.v $xr5, $xr5, $xr6
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; CHECK-NEXT: xvor.v $xr2, $xr2, $xr5
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; CHECK-NEXT: xvand.v $xr1, $xr0, $xr1
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; CHECK-NEXT: xvslli.d $xr1, $xr1, 24
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; CHECK-NEXT: xvand.v $xr3, $xr0, $xr3
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; CHECK-NEXT: xvslli.d $xr3, $xr3, 8
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; CHECK-NEXT: xvor.v $xr1, $xr1, $xr3
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; CHECK-NEXT: xvand.v $xr3, $xr0, $xr4
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; CHECK-NEXT: xvslli.d $xr3, $xr3, 40
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; CHECK-NEXT: xvslli.d $xr0, $xr0, 56
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr3
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr2
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; CHECK-NEXT: xvst $xr0, $a1, 0
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; CHECK-NEXT: ret
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%v = load <4 x i64>, ptr %src
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%res = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %v)
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store <4 x i64> %res, ptr %dst
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ret void
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}
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declare <16 x i16> @llvm.bswap.v16i16(<16 x i16>)
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declare <8 x i32> @llvm.bswap.v8i32(<8 x i32>)
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declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>)

‎llvm/test/CodeGen/LoongArch/lsx/bswap.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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define void @bswap_v8i16(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: bswap_v8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a0, 0
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; CHECK-NEXT: vsrli.h $vr1, $vr0, 8
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; CHECK-NEXT: vslli.h $vr0, $vr0, 8
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; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a1, 0
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; CHECK-NEXT: ret
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%v = load <8 x i16>, ptr %src
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%res = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %v)
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store <8 x i16> %res, ptr %dst
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ret void
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}
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define void @bswap_v4i32(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: bswap_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a0, 0
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; CHECK-NEXT: lu12i.w $a0, 15
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; CHECK-NEXT: ori $a0, $a0, 3840
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; CHECK-NEXT: vreplgr2vr.w $vr1, $a0
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; CHECK-NEXT: vsrli.w $vr2, $vr0, 8
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; CHECK-NEXT: vand.v $vr2, $vr2, $vr1
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; CHECK-NEXT: vsrli.w $vr3, $vr0, 24
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; CHECK-NEXT: vor.v $vr2, $vr2, $vr3
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; CHECK-NEXT: vand.v $vr1, $vr0, $vr1
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; CHECK-NEXT: vslli.w $vr1, $vr1, 8
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; CHECK-NEXT: vslli.w $vr0, $vr0, 24
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; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vor.v $vr0, $vr0, $vr2
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; CHECK-NEXT: vst $vr0, $a1, 0
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; CHECK-NEXT: ret
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%v = load <4 x i32>, ptr %src
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%res = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %v)
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store <4 x i32> %res, ptr %dst
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ret void
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}
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define void @bswap_v2i64(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: bswap_v2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a0, 0
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; CHECK-NEXT: lu12i.w $a0, 4080
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; CHECK-NEXT: vreplgr2vr.d $vr1, $a0
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; CHECK-NEXT: vsrli.d $vr2, $vr0, 24
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; CHECK-NEXT: vand.v $vr2, $vr2, $vr1
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; CHECK-NEXT: lu12i.w $a0, -4096
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; CHECK-NEXT: lu32i.d $a0, 0
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; CHECK-NEXT: vreplgr2vr.d $vr3, $a0
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; CHECK-NEXT: vsrli.d $vr4, $vr0, 8
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; CHECK-NEXT: vand.v $vr4, $vr4, $vr3
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; CHECK-NEXT: vor.v $vr2, $vr4, $vr2
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; CHECK-NEXT: lu12i.w $a0, 15
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; CHECK-NEXT: ori $a0, $a0, 3840
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; CHECK-NEXT: vreplgr2vr.d $vr4, $a0
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; CHECK-NEXT: vsrli.d $vr5, $vr0, 40
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; CHECK-NEXT: vand.v $vr5, $vr5, $vr4
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; CHECK-NEXT: vsrli.d $vr6, $vr0, 56
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; CHECK-NEXT: vor.v $vr5, $vr5, $vr6
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; CHECK-NEXT: vor.v $vr2, $vr2, $vr5
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; CHECK-NEXT: vand.v $vr1, $vr0, $vr1
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; CHECK-NEXT: vslli.d $vr1, $vr1, 24
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; CHECK-NEXT: vand.v $vr3, $vr0, $vr3
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; CHECK-NEXT: vslli.d $vr3, $vr3, 8
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; CHECK-NEXT: vor.v $vr1, $vr1, $vr3
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; CHECK-NEXT: vand.v $vr3, $vr0, $vr4
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; CHECK-NEXT: vslli.d $vr3, $vr3, 40
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; CHECK-NEXT: vslli.d $vr0, $vr0, 56
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; CHECK-NEXT: vor.v $vr0, $vr0, $vr3
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; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vor.v $vr0, $vr0, $vr2
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; CHECK-NEXT: vst $vr0, $a1, 0
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; CHECK-NEXT: ret
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%v = load <2 x i64>, ptr %src
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%res = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %v)
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store <2 x i64> %res, ptr %dst
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ret void
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}
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declare <8 x i16> @llvm.bswap.v8i16(<8 x i16>)
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declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)
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declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>)

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