Skip to content

Commit 558c519

Browse files
authored
[SystemZ] LivePhysRegs to LiveRegUnits (NFC) (#85162)
More conversions from LivePhysRegs to LiveRegUnits
1 parent 0f8a747 commit 558c519

File tree

1 file changed

+10
-6
lines changed

1 file changed

+10
-6
lines changed

llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@
1717
#include "SystemZInstrInfo.h"
1818
#include "SystemZSubtarget.h"
1919
#include "llvm/ADT/Statistic.h"
20-
#include "llvm/CodeGen/LivePhysRegs.h"
20+
#include "llvm/CodeGen/LiveRegUnits.h"
2121
#include "llvm/CodeGen/MachineFunctionPass.h"
2222
#include "llvm/CodeGen/MachineInstrBuilder.h"
2323
using namespace llvm;
@@ -161,7 +161,8 @@ bool SystemZPostRewrite::expandCondMove(MachineBasicBlock &MBB,
161161
assert(DestReg == MI.getOperand(1).getReg() &&
162162
"Expected destination and first source operand to be the same.");
163163

164-
LivePhysRegs LiveRegs(TII->getRegisterInfo());
164+
const TargetRegisterInfo &TRI = TII->getRegisterInfo();
165+
LiveRegUnits LiveRegs(TRI);
165166
LiveRegs.addLiveOuts(MBB);
166167
for (auto I = std::prev(MBB.end()); I != MBBI; --I)
167168
LiveRegs.stepBackward(*I);
@@ -171,15 +172,18 @@ bool SystemZPostRewrite::expandCondMove(MachineBasicBlock &MBB,
171172
MF.insert(std::next(MachineFunction::iterator(MBB)), RestMBB);
172173
RestMBB->splice(RestMBB->begin(), &MBB, MI, MBB.end());
173174
RestMBB->transferSuccessors(&MBB);
174-
for (MCPhysReg R : LiveRegs)
175-
RestMBB->addLiveIn(R);
175+
const BitVector &BV = TRI.getAllocatableSet(MF);
176+
for (Register Reg : BV.set_bits())
177+
if (!LiveRegs.available(Reg))
178+
RestMBB->addLiveIn(Reg);
176179

177180
// Create a new block MoveMBB to hold the move instruction.
178181
MachineBasicBlock *MoveMBB = MF.CreateMachineBasicBlock(BB);
179182
MF.insert(std::next(MachineFunction::iterator(MBB)), MoveMBB);
180183
MoveMBB->addLiveIn(SrcReg);
181-
for (MCPhysReg R : LiveRegs)
182-
MoveMBB->addLiveIn(R);
184+
for (Register Reg : BV.set_bits())
185+
if (!LiveRegs.available(Reg))
186+
MoveMBB->addLiveIn(Reg);
183187

184188
// At the end of MBB, create a conditional branch to RestMBB if the
185189
// condition is false, otherwise fall through to MoveMBB.

0 commit comments

Comments
 (0)