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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 |
| 2 | +; RUN: opt < %s -passes=bounds-checking -S | FileCheck %s --check-prefixes=TR |
| 3 | +; RUN: opt < %s -passes='bounds-checking<trap>' -S | FileCheck %s --check-prefixes=TR |
| 4 | +; RUN: opt < %s -passes='bounds-checking<rt>' -S | FileCheck %s --check-prefixes=RT |
| 5 | +; RUN: opt < %s -passes='bounds-checking<rt-abort>' -S | FileCheck %s --check-prefixes=RTABORT |
| 6 | +; RUN: opt < %s -passes='bounds-checking<min-rt>' -S | FileCheck %s --check-prefixes=MINRT |
| 7 | +; RUN: opt < %s -passes='bounds-checking<min-rt-abort>' -S | FileCheck %s --check-prefixes=MINRTABORT |
| 8 | + |
| 9 | +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" |
| 10 | + |
| 11 | +define void @f1(i64 %x) nounwind { |
| 12 | +; TR-LABEL: define void @f1( |
| 13 | +; TR-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] { |
| 14 | +; TR-NEXT: [[TMP1:%.*]] = mul i64 16, [[X]] |
| 15 | +; TR-NEXT: [[TMP2:%.*]] = alloca i128, i64 [[X]], align 8 |
| 16 | +; TR-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0 |
| 17 | +; TR-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16 |
| 18 | +; TR-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]] |
| 19 | +; TR-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]] |
| 20 | +; TR-NEXT: br i1 [[TMP6]], label %[[TRAP:.*]], label %[[BB7:.*]] |
| 21 | +; TR: [[BB7]]: |
| 22 | +; TR-NEXT: [[TMP8:%.*]] = load i128, ptr [[TMP2]], align 4 |
| 23 | +; TR-NEXT: ret void |
| 24 | +; TR: [[TRAP]]: |
| 25 | +; TR-NEXT: call void @llvm.trap() #[[ATTR2:[0-9]+]] |
| 26 | +; TR-NEXT: unreachable |
| 27 | +; |
| 28 | +; RT-LABEL: define void @f1( |
| 29 | +; RT-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] { |
| 30 | +; RT-NEXT: [[TMP1:%.*]] = mul i64 16, [[X]] |
| 31 | +; RT-NEXT: [[TMP2:%.*]] = alloca i128, i64 [[X]], align 8 |
| 32 | +; RT-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0 |
| 33 | +; RT-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16 |
| 34 | +; RT-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]] |
| 35 | +; RT-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]] |
| 36 | +; RT-NEXT: br i1 [[TMP6]], label %[[TRAP:.*]], label %[[BB7:.*]] |
| 37 | +; RT: [[BB7]]: |
| 38 | +; RT-NEXT: [[TMP8:%.*]] = load i128, ptr [[TMP2]], align 4 |
| 39 | +; RT-NEXT: ret void |
| 40 | +; RT: [[TRAP]]: |
| 41 | +; RT-NEXT: call void @llvm.trap() #[[ATTR2:[0-9]+]] |
| 42 | +; RT-NEXT: unreachable |
| 43 | +; |
| 44 | +; RTABORT-LABEL: define void @f1( |
| 45 | +; RTABORT-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] { |
| 46 | +; RTABORT-NEXT: [[TMP1:%.*]] = mul i64 16, [[X]] |
| 47 | +; RTABORT-NEXT: [[TMP2:%.*]] = alloca i128, i64 [[X]], align 8 |
| 48 | +; RTABORT-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0 |
| 49 | +; RTABORT-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16 |
| 50 | +; RTABORT-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]] |
| 51 | +; RTABORT-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]] |
| 52 | +; RTABORT-NEXT: br i1 [[TMP6]], label %[[TRAP:.*]], label %[[BB7:.*]] |
| 53 | +; RTABORT: [[BB7]]: |
| 54 | +; RTABORT-NEXT: [[TMP8:%.*]] = load i128, ptr [[TMP2]], align 4 |
| 55 | +; RTABORT-NEXT: ret void |
| 56 | +; RTABORT: [[TRAP]]: |
| 57 | +; RTABORT-NEXT: call void @llvm.trap() #[[ATTR2:[0-9]+]] |
| 58 | +; RTABORT-NEXT: unreachable |
| 59 | +; |
| 60 | +; MINRT-LABEL: define void @f1( |
| 61 | +; MINRT-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] { |
| 62 | +; MINRT-NEXT: [[TMP1:%.*]] = mul i64 16, [[X]] |
| 63 | +; MINRT-NEXT: [[TMP2:%.*]] = alloca i128, i64 [[X]], align 8 |
| 64 | +; MINRT-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0 |
| 65 | +; MINRT-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16 |
| 66 | +; MINRT-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]] |
| 67 | +; MINRT-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]] |
| 68 | +; MINRT-NEXT: br i1 [[TMP6]], label %[[TRAP:.*]], label %[[BB7:.*]] |
| 69 | +; MINRT: [[BB7]]: |
| 70 | +; MINRT-NEXT: [[TMP8:%.*]] = load i128, ptr [[TMP2]], align 4 |
| 71 | +; MINRT-NEXT: ret void |
| 72 | +; MINRT: [[TRAP]]: |
| 73 | +; MINRT-NEXT: call void @llvm.trap() #[[ATTR2:[0-9]+]] |
| 74 | +; MINRT-NEXT: unreachable |
| 75 | +; |
| 76 | +; MINRTABORT-LABEL: define void @f1( |
| 77 | +; MINRTABORT-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] { |
| 78 | +; MINRTABORT-NEXT: [[TMP1:%.*]] = mul i64 16, [[X]] |
| 79 | +; MINRTABORT-NEXT: [[TMP2:%.*]] = alloca i128, i64 [[X]], align 8 |
| 80 | +; MINRTABORT-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0 |
| 81 | +; MINRTABORT-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16 |
| 82 | +; MINRTABORT-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]] |
| 83 | +; MINRTABORT-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]] |
| 84 | +; MINRTABORT-NEXT: br i1 [[TMP6]], label %[[TRAP:.*]], label %[[BB7:.*]] |
| 85 | +; MINRTABORT: [[BB7]]: |
| 86 | +; MINRTABORT-NEXT: [[TMP8:%.*]] = load i128, ptr [[TMP2]], align 4 |
| 87 | +; MINRTABORT-NEXT: ret void |
| 88 | +; MINRTABORT: [[TRAP]]: |
| 89 | +; MINRTABORT-NEXT: call void @llvm.trap() #[[ATTR2:[0-9]+]] |
| 90 | +; MINRTABORT-NEXT: unreachable |
| 91 | +; |
| 92 | + %1 = alloca i128, i64 %x |
| 93 | + %3 = load i128, ptr %1, align 4 |
| 94 | + ret void |
| 95 | +} |
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