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[RISCV] Add Sched classes for vector crypto instructions (#90068)
The vector crypto instructions may have different scheduling behavior compared to VALU operations. Instead of using scheduling resources that describe VALU operations, we give these instructions their own scheduling resources. This is similar to what we did for Zb* instructions. The sifive-p670 has vector crypto, so we model behavior for these instructions in the P600SchedModel. The numbers are based off of measurements collected internally. These numbers are a bit old and new measurements show that they may not be fully accurate. It is likely that we will refine these numbers in a follow up patch(s) based on new measurements. This PR is stacked on #89256.
1 parent bab1098 commit 56b8bd7

16 files changed

+830
-375
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

Lines changed: 215 additions & 66 deletions
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‎llvm/lib/Target/RISCV/RISCVSchedRocket.td

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@@ -262,4 +262,5 @@ defm : UnsupportedSchedZfa;
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defm : UnsupportedSchedZfh;
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defm : UnsupportedSchedSFB;
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defm : UnsupportedSchedXsfvcp;
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defm : UnsupportedSchedZvk;
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}

‎llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

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@@ -1298,4 +1298,5 @@ defm : UnsupportedSchedZbc;
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defm : UnsupportedSchedZbkb;
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defm : UnsupportedSchedZbkx;
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defm : UnsupportedSchedZfa;
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defm : UnsupportedSchedZvk;
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}

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td

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@@ -367,4 +367,5 @@ defm : UnsupportedSchedSFB;
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defm : UnsupportedSchedZfa;
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defm : UnsupportedSchedV;
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defm : UnsupportedSchedXsfvcp;
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defm : UnsupportedSchedZvk;
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}

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td

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@@ -748,6 +748,62 @@ foreach mx = SchedMxList in {
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}
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}
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751+
// Vector Crypto
752+
foreach mx = SchedMxList in {
753+
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
754+
defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
755+
// Zvbb
756+
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
757+
defm "" : LMULWriteResMX<"WriteVBREVV", [SiFiveP600VectorArith], mx, IsWorstCase>;
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defm "" : LMULWriteResMX<"WriteVCLZV", [SiFiveP600VectorArith], mx, IsWorstCase>;
759+
defm "" : LMULWriteResMX<"WriteVCPOPV", [SiFiveP600VectorArith], mx, IsWorstCase>;
760+
defm "" : LMULWriteResMX<"WriteVCTZV", [SiFiveP600VectorArith], mx, IsWorstCase>;
761+
defm "" : LMULWriteResMX<"WriteVWSLLV", [SiFiveP600VectorArith], mx, IsWorstCase>;
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defm "" : LMULWriteResMX<"WriteVWSLLX", [SiFiveP600VectorArith], mx, IsWorstCase>;
763+
defm "" : LMULWriteResMX<"WriteVWSLLI", [SiFiveP600VectorArith], mx, IsWorstCase>;
764+
}
765+
// Zvbc
766+
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
767+
defm "" : LMULWriteResMX<"WriteVCLMULV", [SiFiveP600VectorArith], mx, IsWorstCase>;
768+
defm "" : LMULWriteResMX<"WriteVCLMULX", [SiFiveP600VectorArith], mx, IsWorstCase>;
769+
}
770+
// Zvkb
771+
// VANDN uses WriteVIALU[V|X|I]
772+
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
773+
defm "" : LMULWriteResMX<"WriteVBREV8V", [SiFiveP600VectorArith], mx, IsWorstCase>;
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defm "" : LMULWriteResMX<"WriteVREV8V", [SiFiveP600VectorArith], mx, IsWorstCase>;
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defm "" : LMULWriteResMX<"WriteVRotV", [SiFiveP600VectorArith], mx, IsWorstCase>;
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defm "" : LMULWriteResMX<"WriteVRotX", [SiFiveP600VectorArith], mx, IsWorstCase>;
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defm "" : LMULWriteResMX<"WriteVRotI", [SiFiveP600VectorArith], mx, IsWorstCase>;
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}
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// Zvkg
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let Latency = 2, ReleaseAtCycles = [LMulLat] in {
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defm "" : LMULWriteResMX<"WriteVGHSHV", [SiFiveP600VectorArith], mx, IsWorstCase>;
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defm "" : LMULWriteResMX<"WriteVGMULV", [SiFiveP600VectorArith], mx, IsWorstCase>;
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}
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// ZvknhaOrZvknhb
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let Latency = 3, ReleaseAtCycles = [LMulLat] in {
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defm "" : LMULWriteResMX<"WriteVSHA2CHV", [SiFiveP600VectorArith], mx, IsWorstCase>;
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defm "" : LMULWriteResMX<"WriteVSHA2CLV", [SiFiveP600VectorArith], mx, IsWorstCase>;
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defm "" : LMULWriteResMX<"WriteVSHA2MSV", [SiFiveP600VectorArith], mx, IsWorstCase>;
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}
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// Zvkned
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let Latency = 2, ReleaseAtCycles = [LMulLat] in {
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defm "" : LMULWriteResMX<"WriteVAESMVV", [SiFiveP600VectorArith], mx, IsWorstCase>;
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defm "" : LMULWriteResMX<"WriteVAESKF1V", [SiFiveP600VectorArith], mx, IsWorstCase>;
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defm "" : LMULWriteResMX<"WriteVAESKF2V", [SiFiveP600VectorArith], mx, IsWorstCase>;
795+
}
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let Latency = 1, ReleaseAtCycles = [LMulLat] in
797+
defm "" : LMULWriteResMX<"WriteVAESZV", [SiFiveP600VectorArith], mx, IsWorstCase>;
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// Zvksed
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let Latency = 3, ReleaseAtCycles = [LMulLat] in {
800+
defm "" : LMULWriteResMX<"WriteVSM4KV", [SiFiveP600VEXQ0], mx, IsWorstCase>;
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defm "" : LMULWriteResMX<"WriteVSM4RV", [SiFiveP600VEXQ0], mx, IsWorstCase>;
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defm "" : LMULWriteResMX<"WriteVSM3CV", [SiFiveP600VEXQ0], mx, IsWorstCase>;
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defm "" : LMULWriteResMX<"WriteVSM3MEV", [SiFiveP600VEXQ0], mx, IsWorstCase>;
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}
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}
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// Others
752808
def : WriteRes<WriteCSR, [SiFiveP600SYS]>;
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def : WriteRes<WriteNop, []>;
@@ -1032,6 +1088,42 @@ foreach mx = SchedMxList in {
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def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # sew), 0>;
10331089
}
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// Vector Crypto Extensions
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// Zvbb
1093+
defm "" : LMULReadAdvance<"ReadVBREVV", 0>;
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defm "" : LMULReadAdvance<"ReadVCLZV", 0>;
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defm "" : LMULReadAdvance<"ReadVCPOPV", 0>;
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defm "" : LMULReadAdvance<"ReadVCTZV", 0>;
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defm "" : LMULReadAdvance<"ReadVWSLLV", 0>;
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defm "" : LMULReadAdvance<"ReadVWSLLX", 0>;
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// Zvbc
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defm "" : LMULReadAdvance<"ReadVCLMULV", 0>;
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defm "" : LMULReadAdvance<"ReadVCLMULX", 0>;
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// Zvkb
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// VANDN uses ReadVIALU[V|X|I]
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defm "" : LMULReadAdvance<"ReadVBREV8V", 0>;
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defm "" : LMULReadAdvance<"ReadVREV8V", 0>;
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defm "" : LMULReadAdvance<"ReadVRotV", 0>;
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defm "" : LMULReadAdvance<"ReadVRotX", 0>;
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// Zvkg
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defm "" : LMULReadAdvance<"ReadVGHSHV", 0>;
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defm "" : LMULReadAdvance<"ReadVGMULV", 0>;
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// Zvknha or Zvknhb
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defm "" : LMULReadAdvance<"ReadVSHA2CHV", 0>;
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defm "" : LMULReadAdvance<"ReadVSHA2CLV", 0>;
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defm "" : LMULReadAdvance<"ReadVSHA2MSV", 0>;
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// Zvkned
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defm "" : LMULReadAdvance<"ReadVAESMVV", 0>;
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defm "" : LMULReadAdvance<"ReadVAESKF1V", 0>;
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defm "" : LMULReadAdvance<"ReadVAESKF2V", 0>;
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defm "" : LMULReadAdvance<"ReadVAESZV", 0>;
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// Zvksed
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defm "" : LMULReadAdvance<"ReadVSM4KV", 0>;
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defm "" : LMULReadAdvance<"ReadVSM4RV", 0>;
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// Zbksh
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defm "" : LMULReadAdvance<"ReadVSM3CV", 0>;
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defm "" : LMULReadAdvance<"ReadVSM3MEV", 0>;
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10351127
//===----------------------------------------------------------------------===//
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// Unsupported extensions
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defm : UnsupportedSchedZabha;

‎llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td

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@@ -213,4 +213,5 @@ defm : UnsupportedSchedZbkx;
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defm : UnsupportedSchedZfa;
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defm : UnsupportedSchedZfh;
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defm : UnsupportedSchedXsfvcp;
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defm : UnsupportedSchedZvk;
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}

‎llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td

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@@ -312,4 +312,5 @@ defm : UnsupportedSchedZfh;
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defm : UnsupportedSchedSFB;
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defm : UnsupportedSchedZabha;
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defm : UnsupportedSchedXsfvcp;
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defm : UnsupportedSchedZvk;
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}

‎llvm/lib/Target/RISCV/RISCVSchedule.td

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@@ -297,3 +297,4 @@ def : ReadAdvance<ReadAtomicHD, 0>;
297297
include "RISCVScheduleZb.td"
298298
include "RISCVScheduleV.td"
299299
include "RISCVScheduleXSf.td"
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include "RISCVScheduleZvk.td"

‎llvm/lib/Target/RISCV/RISCVScheduleZvk.td

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//=== RISCVScheduleZvk.td - RISC-V Scheduling Definitions Zvk -*- tablegen ===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
7+
//===----------------------------------------------------------------------===//
8+
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/// Define scheduler resources associated with def operands.
10+
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/// Zvbb extension
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defm "" : LMULSchedWrites<"WriteVBREVV">;
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defm "" : LMULSchedWrites<"WriteVCLZV">;
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defm "" : LMULSchedWrites<"WriteVCPOPV">;
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defm "" : LMULSchedWrites<"WriteVCTZV">;
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defm "" : LMULSchedWrites<"WriteVWSLLV">;
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defm "" : LMULSchedWrites<"WriteVWSLLX">;
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defm "" : LMULSchedWrites<"WriteVWSLLI">;
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20+
/// Zvbc extension
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defm "" : LMULSchedWrites<"WriteVCLMULV">;
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defm "" : LMULSchedWrites<"WriteVCLMULX">;
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24+
/// Zvkb extension
25+
// VANDN uses WriteVIALU[V|X|I]
26+
defm "" : LMULSchedWrites<"WriteVBREV8V">;
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defm "" : LMULSchedWrites<"WriteVREV8V">;
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defm "" : LMULSchedWrites<"WriteVRotV">;
29+
defm "" : LMULSchedWrites<"WriteVRotX">;
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defm "" : LMULSchedWrites<"WriteVRotI">;
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32+
/// Zvkg extension
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defm "" : LMULSchedWrites<"WriteVGHSHV">;
34+
defm "" : LMULSchedWrites<"WriteVGMULV">;
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36+
/// Zvknha or Zvknhb extensions
37+
defm "" : LMULSchedWrites<"WriteVSHA2CHV">;
38+
defm "" : LMULSchedWrites<"WriteVSHA2CLV">;
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defm "" : LMULSchedWrites<"WriteVSHA2MSV">;
40+
41+
/// Zvkned extension
42+
defm "" : LMULSchedWrites<"WriteVAESMVV">;
43+
defm "" : LMULSchedWrites<"WriteVAESKF1V">;
44+
defm "" : LMULSchedWrites<"WriteVAESKF2V">;
45+
defm "" : LMULSchedWrites<"WriteVAESZV">;
46+
47+
/// Zvksed extension
48+
defm "" : LMULSchedWrites<"WriteVSM4KV">;
49+
defm "" : LMULSchedWrites<"WriteVSM4RV">;
50+
51+
/// Zvksh extension
52+
defm "" : LMULSchedWrites<"WriteVSM3CV">;
53+
defm "" : LMULSchedWrites<"WriteVSM3MEV">;
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55+
/// Define scheduler resources associated with use operands.
56+
/// Zvbb extension
57+
defm "" : LMULSchedReads<"ReadVBREVV">;
58+
defm "" : LMULSchedReads<"ReadVCLZV">;
59+
defm "" : LMULSchedReads<"ReadVCPOPV">;
60+
defm "" : LMULSchedReads<"ReadVCTZV">;
61+
defm "" : LMULSchedReads<"ReadVWSLLV">;
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defm "" : LMULSchedReads<"ReadVWSLLX">;
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64+
/// Zvbc extension
65+
defm "" : LMULSchedReads<"ReadVCLMULV">;
66+
defm "" : LMULSchedReads<"ReadVCLMULX">;
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68+
/// Zvkb extension
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// VANDN uses ReadVIALU[V|X|I]
70+
defm "" : LMULSchedReads<"ReadVBREV8V">;
71+
defm "" : LMULSchedReads<"ReadVREV8V">;
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defm "" : LMULSchedReads<"ReadVRotV">;
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defm "" : LMULSchedReads<"ReadVRotX">;
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75+
/// Zvkg extension
76+
defm "" : LMULSchedReads<"ReadVGHSHV">;
77+
defm "" : LMULSchedReads<"ReadVGMULV">;
78+
79+
/// Zvknha or Zvknhb extensions
80+
defm "" : LMULSchedReads<"ReadVSHA2CHV">;
81+
defm "" : LMULSchedReads<"ReadVSHA2CLV">;
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defm "" : LMULSchedReads<"ReadVSHA2MSV">;
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84+
/// Zvkned extension
85+
defm "" : LMULSchedReads<"ReadVAESMVV">;
86+
defm "" : LMULSchedReads<"ReadVAESKF1V">;
87+
defm "" : LMULSchedReads<"ReadVAESKF2V">;
88+
defm "" : LMULSchedReads<"ReadVAESZV">;
89+
90+
/// Zvksed extension
91+
defm "" : LMULSchedReads<"ReadVSM4KV">;
92+
defm "" : LMULSchedReads<"ReadVSM4RV">;
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94+
/// Zvksh extension
95+
defm "" : LMULSchedReads<"ReadVSM3CV">;
96+
defm "" : LMULSchedReads<"ReadVSM3MEV">;
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98+
multiclass UnsupportedSchedZvbb {
99+
let Unsupported = true in {
100+
defm "" : LMULWriteRes<"WriteVBREVV", []>;
101+
defm "" : LMULWriteRes<"WriteVCLZV", []>;
102+
defm "" : LMULWriteRes<"WriteVCPOPV", []>;
103+
defm "" : LMULWriteRes<"WriteVCTZV", []>;
104+
defm "" : LMULWriteRes<"WriteVWSLLV", []>;
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defm "" : LMULWriteRes<"WriteVWSLLX", []>;
106+
defm "" : LMULWriteRes<"WriteVWSLLI", []>;
107+
108+
defm "" : LMULReadAdvance<"ReadVBREVV", 0>;
109+
defm "" : LMULReadAdvance<"ReadVCLZV", 0>;
110+
defm "" : LMULReadAdvance<"ReadVCPOPV", 0>;
111+
defm "" : LMULReadAdvance<"ReadVCTZV", 0>;
112+
defm "" : LMULReadAdvance<"ReadVWSLLV", 0>;
113+
defm "" : LMULReadAdvance<"ReadVWSLLX", 0>;
114+
}
115+
}
116+
117+
multiclass UnsupportedSchedZvbc {
118+
let Unsupported = true in {
119+
defm "" : LMULWriteRes<"WriteVCLMULV", []>;
120+
defm "" : LMULWriteRes<"WriteVCLMULX", []>;
121+
122+
defm "" : LMULReadAdvance<"ReadVCLMULV", 0>;
123+
defm "" : LMULReadAdvance<"ReadVCLMULX", 0>;
124+
}
125+
}
126+
127+
multiclass UnsupportedSchedZvkb {
128+
let Unsupported = true in {
129+
defm "" : LMULWriteRes<"WriteVBREV8V", []>;
130+
defm "" : LMULWriteRes<"WriteVREV8V", []>;
131+
defm "" : LMULWriteRes<"WriteVRotV", []>;
132+
defm "" : LMULWriteRes<"WriteVRotX", []>;
133+
defm "" : LMULWriteRes<"WriteVRotI", []>;
134+
135+
defm "" : LMULReadAdvance<"ReadVBREV8V", 0>;
136+
defm "" : LMULReadAdvance<"ReadVREV8V", 0>;
137+
defm "" : LMULReadAdvance<"ReadVRotV", 0>;
138+
defm "" : LMULReadAdvance<"ReadVRotX", 0>;
139+
}
140+
}
141+
142+
multiclass UnsupportedSchedZvkg {
143+
let Unsupported = true in {
144+
defm "" : LMULWriteRes<"WriteVGHSHV", []>;
145+
defm "" : LMULWriteRes<"WriteVGMULV", []>;
146+
147+
defm "" : LMULReadAdvance<"ReadVGHSHV", 0>;
148+
defm "" : LMULReadAdvance<"ReadVGMULV", 0>;
149+
}
150+
}
151+
152+
multiclass UnsupportedSchedZvknhaOrZvknhb {
153+
let Unsupported = true in {
154+
defm "" : LMULWriteRes<"WriteVSHA2CHV", []>;
155+
defm "" : LMULWriteRes<"WriteVSHA2CLV", []>;
156+
defm "" : LMULWriteRes<"WriteVSHA2MSV", []>;
157+
158+
defm "" : LMULReadAdvance<"ReadVSHA2CHV", 0>;
159+
defm "" : LMULReadAdvance<"ReadVSHA2CLV", 0>;
160+
defm "" : LMULReadAdvance<"ReadVSHA2MSV", 0>;
161+
}
162+
}
163+
164+
multiclass UnsupportedSchedZvkned {
165+
let Unsupported = true in {
166+
defm "" : LMULWriteRes<"WriteVAESMVV", []>;
167+
defm "" : LMULWriteRes<"WriteVAESKF1V", []>;
168+
defm "" : LMULWriteRes<"WriteVAESKF2V", []>;
169+
defm "" : LMULWriteRes<"WriteVAESZV", []>;
170+
171+
defm "" : LMULReadAdvance<"ReadVAESMVV", 0>;
172+
defm "" : LMULReadAdvance<"ReadVAESKF1V", 0>;
173+
defm "" : LMULReadAdvance<"ReadVAESKF2V", 0>;
174+
defm "" : LMULReadAdvance<"ReadVAESZV", 0>;
175+
}
176+
}
177+
178+
multiclass UnsupportedSchedZvksed {
179+
let Unsupported = true in {
180+
defm "" : LMULWriteRes<"WriteVSM4KV", []>;
181+
defm "" : LMULWriteRes<"WriteVSM4RV", []>;
182+
183+
defm "" : LMULReadAdvance<"ReadVSM4KV", 0>;
184+
defm "" : LMULReadAdvance<"ReadVSM4RV", 0>;
185+
}
186+
}
187+
188+
multiclass UnsupportedSchedZvksh {
189+
let Unsupported = true in {
190+
defm "" : LMULWriteRes<"WriteVSM3CV", []>;
191+
defm "" : LMULWriteRes<"WriteVSM3MEV", []>;
192+
193+
defm "" : LMULReadAdvance<"ReadVSM3CV", 0>;
194+
defm "" : LMULReadAdvance<"ReadVSM3MEV", 0>;
195+
}
196+
}
197+
198+
// Helper class to define all RISC-V Vector Crypto extensions as unsupported
199+
multiclass UnsupportedSchedZvk {
200+
defm "" : UnsupportedSchedZvbb;
201+
defm "" : UnsupportedSchedZvbc;
202+
defm "" : UnsupportedSchedZvkb;
203+
defm "" : UnsupportedSchedZvkg;
204+
defm "" : UnsupportedSchedZvknhaOrZvknhb;
205+
defm "" : UnsupportedSchedZvkned;
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defm "" : UnsupportedSchedZvksed;
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defm "" : UnsupportedSchedZvksh;
208+
}

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