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[AArch64] Separate PNR into it's own Register Class
This patch separates PNR registers into their own register class instead of sharing a register class with PPR registers. This primarily allows us to return more accurate register classes when applying assembly constraints, but also more protection from supplying an incorrect predicate type to an invalid register operand.
1 parent 7fcbb64 commit 56d2802

21 files changed

+364
-143
lines changed

‎llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -974,6 +974,8 @@ bool AArch64AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
974974
RegClass = &AArch64::ZPRRegClass;
975975
} else if (AArch64::PPRRegClass.contains(Reg)) {
976976
RegClass = &AArch64::PPRRegClass;
977+
} else if (AArch64::PNRRegClass.contains(Reg)) {
978+
RegClass = &AArch64::PNRRegClass;
977979
} else {
978980
RegClass = &AArch64::FPR128RegClass;
979981
AltName = AArch64::vreg;

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3668,6 +3668,39 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
36683668
return;
36693669
}
36703670

3671+
if (AArch64::PNRRegClass.contains(DestReg) &&
3672+
AArch64::PPRRegClass.contains(SrcReg)) {
3673+
assert((Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
3674+
"Unexpected predicate-as-counter register.");
3675+
// Copy from pX to pnX is a no-op
3676+
if ((DestReg.id() - AArch64::PN0) == (SrcReg.id() - AArch64::P0))
3677+
return;
3678+
MCRegister PPRDestReg = (DestReg - AArch64::PN0) + AArch64::P0;
3679+
BuildMI(MBB, I, DL, get(AArch64::ORR_PPzPP), PPRDestReg)
3680+
.addReg(SrcReg)
3681+
.addReg(SrcReg)
3682+
.addReg(SrcReg, getKillRegState(KillSrc))
3683+
.addDef(DestReg, RegState::Implicit);
3684+
return;
3685+
}
3686+
3687+
if (AArch64::PPRRegClass.contains(DestReg) &&
3688+
AArch64::PNRRegClass.contains(SrcReg)) {
3689+
assert((Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
3690+
"Unexpected predicate-as-counter register.");
3691+
// Copy from pnX to pX is a no-op
3692+
if ((DestReg.id() - AArch64::P0) == (SrcReg.id() - AArch64::PN0))
3693+
return;
3694+
MCRegister PNRDestReg = (DestReg - AArch64::P0) + AArch64::PN0;
3695+
MCRegister PPRSrcReg = (SrcReg - AArch64::PN0) + AArch64::P0;
3696+
BuildMI(MBB, I, DL, get(AArch64::ORR_PPzPP), DestReg)
3697+
.addReg(PPRSrcReg)
3698+
.addReg(PPRSrcReg)
3699+
.addReg(PPRSrcReg, getKillRegState(KillSrc))
3700+
.addDef(PNRDestReg, RegState::Implicit);
3701+
return;
3702+
}
3703+
36713704
// Copy a Z register by ORRing with itself.
36723705
if (AArch64::ZPRRegClass.contains(DestReg) &&
36733706
AArch64::ZPRRegClass.contains(SrcReg)) {
@@ -3961,6 +3994,7 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
39613994
MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
39623995
unsigned Opc = 0;
39633996
bool Offset = true;
3997+
MCRegister PNRReg = MCRegister::NoRegister;
39643998
unsigned StackID = TargetStackID::Default;
39653999
switch (TRI->getSpillSize(*RC)) {
39664000
case 1:
@@ -3975,6 +4009,12 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
39754009
"Unexpected register store without SVE store instructions");
39764010
Opc = AArch64::STR_PXI;
39774011
StackID = TargetStackID::ScalableVector;
4012+
} else if (AArch64::PNRRegClass.hasSubClassEq(RC)) {
4013+
assert((Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
4014+
"Unexpected register store without SVE2p1 or SME2");
4015+
SrcReg = (SrcReg - AArch64::PN0) + AArch64::P0;
4016+
Opc = AArch64::STR_PXI;
4017+
StackID = TargetStackID::ScalableVector;
39784018
}
39794019
break;
39804020
case 4:
@@ -4081,6 +4121,8 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
40814121

40824122
if (Offset)
40834123
MI.addImm(0);
4124+
if (PNRReg.isValid())
4125+
MI.addDef(PNRReg, RegState::Implicit);
40844126
MI.addMemOperand(MMO);
40854127
}
40864128

@@ -4125,6 +4167,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
41254167
unsigned Opc = 0;
41264168
bool Offset = true;
41274169
unsigned StackID = TargetStackID::Default;
4170+
MCRegister PNRReg = MCRegister::NoRegister;
41284171
switch (TRI->getSpillSize(*RC)) {
41294172
case 1:
41304173
if (AArch64::FPR8RegClass.hasSubClassEq(RC))
@@ -4138,6 +4181,13 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
41384181
"Unexpected register load without SVE load instructions");
41394182
Opc = AArch64::LDR_PXI;
41404183
StackID = TargetStackID::ScalableVector;
4184+
} else if (AArch64::PNRRegClass.hasSubClassEq(RC)) {
4185+
assert((Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
4186+
"Unexpected register load without SVE2p1 or SME2");
4187+
PNRReg = DestReg;
4188+
DestReg = (DestReg - AArch64::PN0) + AArch64::P0;
4189+
Opc = AArch64::LDR_PXI;
4190+
StackID = TargetStackID::ScalableVector;
41414191
}
41424192
break;
41434193
case 4:
@@ -4244,6 +4294,8 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
42444294
.addFrameIndex(FI);
42454295
if (Offset)
42464296
MI.addImm(0);
4297+
if (PNRReg.isValid())
4298+
MI.addDef(PNRReg, RegState::Implicit);
42474299
MI.addMemOperand(MMO);
42484300
}
42494301

‎llvm/lib/Target/AArch64/AArch64RegisterInfo.td

Lines changed: 106 additions & 66 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,8 @@ let Namespace = "AArch64" in {
5151
def zasubd1 : SubRegIndex<256>; // (16 x 16)/8 bytes = 256 bits
5252
def zasubq0 : SubRegIndex<128>; // (16 x 16)/16 bytes = 128 bits
5353
def zasubq1 : SubRegIndex<128>; // (16 x 16)/16 bytes = 128 bits
54+
55+
def psub : SubRegIndex<16>;
5456
}
5557

5658
let Namespace = "AArch64" in {
@@ -763,23 +765,43 @@ def GPR64x8 : RegisterOperand<GPR64x8Class, "printGPR64x8"> {
763765

764766
//===----- END: v8.7a accelerator extension register operands -------------===//
765767

768+
// SVE predicate-as-counter registers
769+
def PN0 : AArch64Reg<0, "pn0">, DwarfRegNum<[48]>;
770+
def PN1 : AArch64Reg<1, "pn1">, DwarfRegNum<[49]>;
771+
def PN2 : AArch64Reg<2, "pn2">, DwarfRegNum<[50]>;
772+
def PN3 : AArch64Reg<3, "pn3">, DwarfRegNum<[51]>;
773+
def PN4 : AArch64Reg<4, "pn4">, DwarfRegNum<[52]>;
774+
def PN5 : AArch64Reg<5, "pn5">, DwarfRegNum<[53]>;
775+
def PN6 : AArch64Reg<6, "pn6">, DwarfRegNum<[54]>;
776+
def PN7 : AArch64Reg<7, "pn7">, DwarfRegNum<[55]>;
777+
def PN8 : AArch64Reg<8, "pn8">, DwarfRegNum<[56]>;
778+
def PN9 : AArch64Reg<9, "pn9">, DwarfRegNum<[57]>;
779+
def PN10 : AArch64Reg<10, "pn10">, DwarfRegNum<[58]>;
780+
def PN11 : AArch64Reg<11, "pn11">, DwarfRegNum<[59]>;
781+
def PN12 : AArch64Reg<12, "pn12">, DwarfRegNum<[60]>;
782+
def PN13 : AArch64Reg<13, "pn13">, DwarfRegNum<[61]>;
783+
def PN14 : AArch64Reg<14, "pn14">, DwarfRegNum<[62]>;
784+
def PN15 : AArch64Reg<15, "pn15">, DwarfRegNum<[63]>;
785+
766786
// SVE predicate registers
767-
def P0 : AArch64Reg<0, "p0">, DwarfRegNum<[48]>;
768-
def P1 : AArch64Reg<1, "p1">, DwarfRegNum<[49]>;
769-
def P2 : AArch64Reg<2, "p2">, DwarfRegNum<[50]>;
770-
def P3 : AArch64Reg<3, "p3">, DwarfRegNum<[51]>;
771-
def P4 : AArch64Reg<4, "p4">, DwarfRegNum<[52]>;
772-
def P5 : AArch64Reg<5, "p5">, DwarfRegNum<[53]>;
773-
def P6 : AArch64Reg<6, "p6">, DwarfRegNum<[54]>;
774-
def P7 : AArch64Reg<7, "p7">, DwarfRegNum<[55]>;
775-
def P8 : AArch64Reg<8, "p8">, DwarfRegNum<[56]>;
776-
def P9 : AArch64Reg<9, "p9">, DwarfRegNum<[57]>;
777-
def P10 : AArch64Reg<10, "p10">, DwarfRegNum<[58]>;
778-
def P11 : AArch64Reg<11, "p11">, DwarfRegNum<[59]>;
779-
def P12 : AArch64Reg<12, "p12">, DwarfRegNum<[60]>;
780-
def P13 : AArch64Reg<13, "p13">, DwarfRegNum<[61]>;
781-
def P14 : AArch64Reg<14, "p14">, DwarfRegNum<[62]>;
782-
def P15 : AArch64Reg<15, "p15">, DwarfRegNum<[63]>;
787+
let SubRegIndices = [psub] in {
788+
def P0 : AArch64Reg<0, "p0", [PN0]>, DwarfRegAlias<PN0>;
789+
def P1 : AArch64Reg<1, "p1", [PN1]>, DwarfRegAlias<PN1>;
790+
def P2 : AArch64Reg<2, "p2", [PN2]>, DwarfRegAlias<PN2>;
791+
def P3 : AArch64Reg<3, "p3", [PN3]>, DwarfRegAlias<PN3>;
792+
def P4 : AArch64Reg<4, "p4", [PN4]>, DwarfRegAlias<PN4>;
793+
def P5 : AArch64Reg<5, "p5", [PN5]>, DwarfRegAlias<PN5>;
794+
def P6 : AArch64Reg<6, "p6", [PN6]>, DwarfRegAlias<PN6>;
795+
def P7 : AArch64Reg<7, "p7", [PN7]>, DwarfRegAlias<PN7>;
796+
def P8 : AArch64Reg<8, "p8", [PN8]>, DwarfRegAlias<PN8>;
797+
def P9 : AArch64Reg<9, "p9", [PN9]>, DwarfRegAlias<PN9>;
798+
def P10 : AArch64Reg<10, "p10", [PN10]>, DwarfRegAlias<PN10>;
799+
def P11 : AArch64Reg<11, "p11", [PN11]>, DwarfRegAlias<PN11>;
800+
def P12 : AArch64Reg<12, "p12", [PN12]>, DwarfRegAlias<PN12>;
801+
def P13 : AArch64Reg<13, "p13", [PN13]>, DwarfRegAlias<PN13>;
802+
def P14 : AArch64Reg<14, "p14", [PN14]>, DwarfRegAlias<PN14>;
803+
def P15 : AArch64Reg<15, "p15", [PN15]>, DwarfRegAlias<PN15>;
804+
}
783805

784806
// SVE variable-size vector registers
785807
let SubRegIndices = [zsub] in {
@@ -842,8 +864,6 @@ class SVERegOp <string Suffix, AsmOperandClass C,
842864
let ParserMatchClass = C;
843865
}
844866

845-
class PPRRegOp <string Suffix, AsmOperandClass C, ElementSizeEnum Size,
846-
RegisterClass RC> : SVERegOp<Suffix, C, Size, RC> {}
847867
class ZPRRegOp <string Suffix, AsmOperandClass C, ElementSizeEnum Size,
848868
RegisterClass RC> : SVERegOp<Suffix, C, Size, RC> {}
849869

@@ -852,7 +872,7 @@ class ZPRRegOp <string Suffix, AsmOperandClass C, ElementSizeEnum Size,
852872
// SVE predicate register classes.
853873
class PPRClass<int firstreg, int lastreg> : RegisterClass<
854874
"AArch64",
855-
[ nxv16i1, nxv8i1, nxv4i1, nxv2i1, nxv1i1, aarch64svcount ], 16,
875+
[ nxv16i1, nxv8i1, nxv4i1, nxv2i1, nxv1i1 ], 16,
856876
(sequence "P%u", firstreg, lastreg)> {
857877
let Size = 16;
858878
}
@@ -870,69 +890,89 @@ class PPRAsmOperand <string name, string RegClass, int Width>: AsmOperandClass {
870890
let ParserMethod = "tryParseSVEPredicateVector<RegKind::SVEPredicateVector>";
871891
}
872892

873-
def PPRAsmOpAny : PPRAsmOperand<"PredicateAny", "PPR", 0>;
874-
def PPRAsmOp8 : PPRAsmOperand<"PredicateB", "PPR", 8>;
875-
def PPRAsmOp16 : PPRAsmOperand<"PredicateH", "PPR", 16>;
876-
def PPRAsmOp32 : PPRAsmOperand<"PredicateS", "PPR", 32>;
877-
def PPRAsmOp64 : PPRAsmOperand<"PredicateD", "PPR", 64>;
878-
879-
def PPRAny : PPRRegOp<"", PPRAsmOpAny, ElementSizeNone, PPR>;
880-
def PPR8 : PPRRegOp<"b", PPRAsmOp8, ElementSizeB, PPR>;
881-
def PPR16 : PPRRegOp<"h", PPRAsmOp16, ElementSizeH, PPR>;
882-
def PPR32 : PPRRegOp<"s", PPRAsmOp32, ElementSizeS, PPR>;
883-
def PPR64 : PPRRegOp<"d", PPRAsmOp64, ElementSizeD, PPR>;
884-
893+
def PPRAsmOpAny : PPRAsmOperand<"PredicateAny", "PPR", 0>;
894+
def PPRAsmOp8 : PPRAsmOperand<"PredicateB", "PPR", 8>;
895+
def PPRAsmOp16 : PPRAsmOperand<"PredicateH", "PPR", 16>;
896+
def PPRAsmOp32 : PPRAsmOperand<"PredicateS", "PPR", 32>;
897+
def PPRAsmOp64 : PPRAsmOperand<"PredicateD", "PPR", 64>;
885898
def PPRAsmOp3bAny : PPRAsmOperand<"Predicate3bAny", "PPR_3b", 0>;
886899

900+
class PPRRegOp <string Suffix, AsmOperandClass C, ElementSizeEnum Size,
901+
RegisterClass RC> : SVERegOp<Suffix, C, Size, RC> {}
902+
903+
def PPRAny : PPRRegOp<"", PPRAsmOpAny, ElementSizeNone, PPR>;
904+
def PPR8 : PPRRegOp<"b", PPRAsmOp8, ElementSizeB, PPR>;
905+
def PPR16 : PPRRegOp<"h", PPRAsmOp16, ElementSizeH, PPR>;
906+
def PPR32 : PPRRegOp<"s", PPRAsmOp32, ElementSizeS, PPR>;
907+
def PPR64 : PPRRegOp<"d", PPRAsmOp64, ElementSizeD, PPR>;
887908
def PPR3bAny : PPRRegOp<"", PPRAsmOp3bAny, ElementSizeNone, PPR_3b>;
888909

910+
class PNRClass<int firstreg, int lastreg> : RegisterClass<
911+
"AArch64",
912+
[ aarch64svcount ], 16,
913+
(sequence "PN%u", firstreg, lastreg)> {
914+
let Size = 16;
915+
}
916+
917+
def PNR : PNRClass<0, 15>;
918+
def PNR_p8to15 : PNRClass<8, 15>;
889919

890920
// SVE predicate-as-counter operand
891-
class PNRAsmOperand<string name, string RegClass, int Width>
892-
: PPRAsmOperand<name, RegClass, Width> {
921+
class PNRAsmOperand<string name, string RegClass, int Width>: AsmOperandClass {
922+
let Name = "SVE" # name # "Reg";
893923
let PredicateMethod = "isSVEPredicateAsCounterRegOfWidth<"
894924
# Width # ", " # "AArch64::"
895925
# RegClass # "RegClassID>";
896926
let DiagnosticType = "InvalidSVE" # name # "Reg";
927+
let RenderMethod = "addRegOperands";
897928
let ParserMethod = "tryParseSVEPredicateVector<RegKind::SVEPredicateAsCounter>";
898929
}
899930

900-
class PNRRegOp<string Suffix, AsmOperandClass C, int EltSize, RegisterClass RC>
901-
: PPRRegOp<Suffix, C, ElementSizeNone, RC> {
902-
let PrintMethod = "printPredicateAsCounter<" # EltSize # ">";
931+
let RenderMethod = "addPNRasPPRRegOperands" in {
932+
def PNRasPPROpAny : PNRAsmOperand<"PNRasPPRPredicateAny", "PNR", 0>;
933+
def PNRasPPROp8 : PNRAsmOperand<"PNRasPPRPredicateB", "PNR", 8>;
903934
}
904935

905-
def PNRAsmOpAny: PNRAsmOperand<"PNPredicateAny", "PPR", 0>;
906-
def PNRAsmOp8 : PNRAsmOperand<"PNPredicateB", "PPR", 8>;
907-
def PNRAsmOp16 : PNRAsmOperand<"PNPredicateH", "PPR", 16>;
908-
def PNRAsmOp32 : PNRAsmOperand<"PNPredicateS", "PPR", 32>;
909-
def PNRAsmOp64 : PNRAsmOperand<"PNPredicateD", "PPR", 64>;
910-
911-
def PNRAny : PNRRegOp<"", PNRAsmOpAny, 0, PPR>;
912-
def PNR8 : PNRRegOp<"b", PNRAsmOp8, 8, PPR>;
913-
def PNR16 : PNRRegOp<"h", PNRAsmOp16, 16, PPR>;
914-
def PNR32 : PNRRegOp<"s", PNRAsmOp32, 32, PPR>;
915-
def PNR64 : PNRRegOp<"d", PNRAsmOp64, 64, PPR>;
916-
917-
class PNRP8to15RegOp<string Suffix, AsmOperandClass C, int EltSize, RegisterClass RC>
918-
: PPRRegOp<Suffix, C, ElementSizeNone, RC> {
919-
let PrintMethod = "printPredicateAsCounter<" # EltSize # ">";
920-
let EncoderMethod = "EncodePPR_p8to15";
921-
let DecoderMethod = "DecodePPR_p8to15RegisterClass";
922-
}
923-
924-
def PNRAsmAny_p8to15 : PNRAsmOperand<"PNPredicateAny_p8to15", "PPR_p8to15", 0>;
925-
def PNRAsmOp8_p8to15 : PNRAsmOperand<"PNPredicateB_p8to15", "PPR_p8to15", 8>;
926-
def PNRAsmOp16_p8to15 : PNRAsmOperand<"PNPredicateH_p8to15", "PPR_p8to15", 16>;
927-
def PNRAsmOp32_p8to15 : PNRAsmOperand<"PNPredicateS_p8to15", "PPR_p8to15", 32>;
928-
def PNRAsmOp64_p8to15 : PNRAsmOperand<"PNPredicateD_p8to15", "PPR_p8to15", 64>;
929-
930-
def PNRAny_p8to15 : PNRP8to15RegOp<"", PNRAsmAny_p8to15, 0, PPR_p8to15>;
931-
def PNR8_p8to15 : PNRP8to15RegOp<"b", PNRAsmOp8_p8to15, 8, PPR_p8to15>;
932-
def PNR16_p8to15 : PNRP8to15RegOp<"h", PNRAsmOp16_p8to15, 16, PPR_p8to15>;
933-
def PNR32_p8to15 : PNRP8to15RegOp<"s", PNRAsmOp32_p8to15, 32, PPR_p8to15>;
934-
def PNR64_p8to15 : PNRP8to15RegOp<"d", PNRAsmOp64_p8to15, 64, PPR_p8to15>;
936+
class PNRasPPRRegOp<string Suffix, AsmOperandClass C, ElementSizeEnum Size,
937+
RegisterClass RC> : SVERegOp<Suffix, C, Size, RC> {}
935938

939+
def PNRasPPRAny : PNRasPPRRegOp<"", PNRasPPROpAny, ElementSizeNone, PPR>;
940+
def PNRasPPR8 : PNRasPPRRegOp<"b", PNRasPPROp8, ElementSizeB, PPR>;
941+
942+
def PNRAsmOpAny: PNRAsmOperand<"PNPredicateAny", "PNR", 0>;
943+
def PNRAsmOp8 : PNRAsmOperand<"PNPredicateB", "PNR", 8>;
944+
def PNRAsmOp16 : PNRAsmOperand<"PNPredicateH", "PNR", 16>;
945+
def PNRAsmOp32 : PNRAsmOperand<"PNPredicateS", "PNR", 32>;
946+
def PNRAsmOp64 : PNRAsmOperand<"PNPredicateD", "PNR", 64>;
947+
948+
class PNRRegOp<string Suffix, AsmOperandClass C, int Size, RegisterClass RC>
949+
: SVERegOp<Suffix, C, ElementSizeNone, RC> {
950+
let PrintMethod = "printPredicateAsCounter<" # Size # ">";
951+
}
952+
def PNRAny : PNRRegOp<"", PNRAsmOpAny, 0, PNR>;
953+
def PNR8 : PNRRegOp<"b", PNRAsmOp8, 8, PNR>;
954+
def PNR16 : PNRRegOp<"h", PNRAsmOp16, 16, PNR>;
955+
def PNR32 : PNRRegOp<"s", PNRAsmOp32, 32, PNR>;
956+
def PNR64 : PNRRegOp<"d", PNRAsmOp64, 64, PNR>;
957+
958+
def PNRAsmAny_p8to15 : PNRAsmOperand<"PNPredicateAny_p8to15", "PNR_p8to15", 0>;
959+
def PNRAsmOp8_p8to15 : PNRAsmOperand<"PNPredicateB_p8to15", "PNR_p8to15", 8>;
960+
def PNRAsmOp16_p8to15 : PNRAsmOperand<"PNPredicateH_p8to15", "PNR_p8to15", 16>;
961+
def PNRAsmOp32_p8to15 : PNRAsmOperand<"PNPredicateS_p8to15", "PNR_p8to15", 32>;
962+
def PNRAsmOp64_p8to15 : PNRAsmOperand<"PNPredicateD_p8to15", "PNR_p8to15", 64>;
963+
964+
class PNRP8to15RegOp<string Suffix, AsmOperandClass C, int Width, RegisterClass RC>
965+
: SVERegOp<Suffix, C, ElementSizeNone, RC> {
966+
let PrintMethod = "printPredicateAsCounter<" # Width # ">";
967+
let EncoderMethod = "EncodePNR_p8to15";
968+
let DecoderMethod = "DecodePNR_p8to15RegisterClass";
969+
}
970+
971+
def PNRAny_p8to15 : PNRP8to15RegOp<"", PNRAsmAny_p8to15, 0, PNR_p8to15>;
972+
def PNR8_p8to15 : PNRP8to15RegOp<"b", PNRAsmOp8_p8to15, 8, PNR_p8to15>;
973+
def PNR16_p8to15 : PNRP8to15RegOp<"h", PNRAsmOp16_p8to15, 16, PNR_p8to15>;
974+
def PNR32_p8to15 : PNRP8to15RegOp<"s", PNRAsmOp32_p8to15, 32, PNR_p8to15>;
975+
def PNR64_p8to15 : PNRP8to15RegOp<"d", PNRAsmOp64_p8to15, 64, PNR_p8to15>;
936976

937977
let Namespace = "AArch64" in {
938978
def psub0 : SubRegIndex<16, -1>;

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -2544,8 +2544,8 @@ let Predicates = [HasSVEorSME] in {
25442544
def : Pat<(nxv4f32 (bitconvert (nxv8bf16 ZPR:$src))), (nxv4f32 ZPR:$src)>;
25452545
def : Pat<(nxv2f64 (bitconvert (nxv8bf16 ZPR:$src))), (nxv2f64 ZPR:$src)>;
25462546

2547-
def : Pat<(nxv16i1 (bitconvert (aarch64svcount PPR:$src))), (nxv16i1 PPR:$src)>;
2548-
def : Pat<(aarch64svcount (bitconvert (nxv16i1 PPR:$src))), (aarch64svcount PPR:$src)>;
2547+
def : Pat<(nxv16i1 (bitconvert (aarch64svcount PNR:$src))), (nxv16i1 PPR:$src)>;
2548+
def : Pat<(aarch64svcount (bitconvert (nxv16i1 PPR:$src))), (aarch64svcount PNR:$src)>;
25492549
}
25502550

25512551
// These allow casting from/to unpacked predicate types.
@@ -3852,9 +3852,9 @@ defm STNT1D_4Z_IMM : sve2p1_mem_cst_si_4z<"stnt1d", 0b11, 0b1, ZZZZ_d_mul_r>;
38523852
multiclass store_pn_x2<ValueType Ty, SDPatternOperator Store,
38533853
Instruction RegImmInst> {
38543854
def : Pat<(Store (Ty ZPR:$vec0), (Ty ZPR:$vec1),
3855-
(aarch64svcount PPR:$PNg), GPR64:$base),
3855+
(aarch64svcount PNR:$PNg), GPR64:$base),
38563856
(RegImmInst (REG_SEQUENCE ZPR2Mul2, Ty:$vec0, zsub0, Ty:$vec1, zsub1),
3857-
PPR:$PNg, GPR64:$base, (i64 0))>;
3857+
PNR:$PNg, GPR64:$base, (i64 0))>;
38583858
}
38593859

38603860
// Stores of 2 consecutive vectors
@@ -3878,10 +3878,10 @@ defm : store_pn_x2<nxv2f64, int_aarch64_sve_stnt1_pn_x2, STNT1D_2Z_IMM>;
38783878
multiclass store_pn_x4<ValueType Ty, SDPatternOperator Store,
38793879
Instruction RegImmInst> {
38803880
def : Pat<(Store (Ty ZPR:$vec0), (Ty ZPR:$vec1), (Ty ZPR:$vec2), (Ty ZPR:$vec3),
3881-
(aarch64svcount PPR:$PNg), GPR64:$base),
3881+
(aarch64svcount PNR:$PNg), GPR64:$base),
38823882
(RegImmInst (REG_SEQUENCE ZPR4Mul4, Ty:$vec0, zsub0, Ty:$vec1, zsub1,
38833883
Ty:$vec2, zsub2, Ty:$vec3, zsub3),
3884-
PPR:$PNg, GPR64:$base, (i64 0))>;
3884+
PNR:$PNg, GPR64:$base, (i64 0))>;
38853885
}
38863886

38873887
// Stores of 4 consecutive vectors
@@ -3923,19 +3923,19 @@ defm WHILELS_CXX : sve2p1_int_while_rr_pn<"whilels", 0b111>;
39233923
// Aliases for existing SVE instructions for which predicate-as-counter are
39243924
// accepted as an operand to the instruction
39253925
def : InstAlias<"ldr $Pt, [$Rn, $imm9, mul vl]",
3926-
(LDR_PXI PNRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), 0>;
3926+
(LDR_PXI PNRasPPRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), 0>;
39273927
def : InstAlias<"ldr $Pt, [$Rn]",
3928-
(LDR_PXI PNRAny:$Pt, GPR64sp:$Rn, 0), 0>;
3928+
(LDR_PXI PNRasPPRAny:$Pt, GPR64sp:$Rn, 0), 0>;
39293929

39303930
def : InstAlias<"str $Pt, [$Rn, $imm9, mul vl]",
3931-
(STR_PXI PNRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), 0>;
3931+
(STR_PXI PNRasPPRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), 0>;
39323932
def : InstAlias<"str $Pt, [$Rn]",
3933-
(STR_PXI PNRAny:$Pt, GPR64sp:$Rn, 0), 0>;
3933+
(STR_PXI PNRasPPRAny:$Pt, GPR64sp:$Rn, 0), 0>;
39343934

39353935
def : InstAlias<"mov $Pd, $Pn",
3936-
(ORR_PPzPP PNR8:$Pd, PNR8:$Pn, PNR8:$Pn, PNR8:$Pn), 0>;
3936+
(ORR_PPzPP PNRasPPR8:$Pd, PNRasPPR8:$Pn, PNRasPPR8:$Pn, PNRasPPR8:$Pn), 0>;
39373937

3938-
def : InstAlias<"pfalse\t$Pd", (PFALSE PNR8:$Pd), 0>;
3938+
def : InstAlias<"pfalse\t$Pd", (PFALSE PNRasPPR8:$Pd), 0>;
39393939

39403940
} // End HasSVE2p1_or_HasSME2
39413941

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