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[LLVM][NVPTX] Add codegen support for tcgen05.{ld, st} instructions
This commit adds support for tcgen05.{ld, st} instructions with lit tests under tcgen05-ld.ll and tcgen05-st.ll and intrinsics documentation under NVPTXUsage.rst
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‎llvm/docs/NVPTXUsage.rst

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@@ -1175,6 +1175,101 @@ For more information, refer to the PTX ISA
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`<https://docs.nvidia.com/cuda/parallel-thread-execution/#tensorcore-5th-generation-instructions-tcgen05-fence>`_.
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'``llvm.nvvm.tcgen05.ld.*``'
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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.. code-block:: llvm
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declare <n x i32> @llvm.nvvm.tcgen05.ld.<shape>.<num>(ptr addrspace(6) %tmem_addr, i1 %pack)
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declare <n x i32> @llvm.nvvm.tcgen05.ld.16x32bx2.<num>(ptr addrspace(6) %tmem_addr, i64 %offset, i1 %pack)
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Overview:
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"""""""""
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This group of intrinsics asynchronously load data from the Tensor Memory at the location specified
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by the 32-bit address operand `tmem_addr` into the destination registers, collectively across all threads
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of the warps.
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All the threads in the warp must specify the same value of `tmem_addr`, which must be the base address
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of the collective load operation. Otherwise, the behavior is undefined.
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The `shape` qualifier and the `num` qualifier together determines the total dimension of the data ('n') which
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is loaded from the Tensor Memory. The `shape` qualifier indicates the base dimension of data. The `num` qualifier
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indicates the repeat factor on the base dimension resulting in the total dimension of the data that is accessed.
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Allowed values for the 'num' are `x1, x2, x4, x8, x16, x32, x64, x128`.
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Allowed values for the 'shape' in the first intrinsic are `16x64b, 16x128b, 16x256b, 32x32b`.
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Allowed value for the 'shape' in the second intrinsic is `16x32bx2`.
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The result of the intrinsic is a vector consisting of one or more 32-bit registers derived from `shape` and
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`num` as shown below.
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=========== ========================= ========== ==========
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num/shape 16x32bx2/16x64b/32x32b 16x128b 16x256b
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=========== ========================= ========== ==========
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x1 1 2 4
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x2 2 4 8
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x4 4 8 16
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x8 8 16 32
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x16 16 32 64
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x32 32 64 128
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x64 64 128 NA
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x128 128 NA NA
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=========== ========================= ========== ==========
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The last argument `i1 %pack` is a compile-time constant which when set, indicates that the adjacent columns are packed into a single 32-bit element during the load
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For more information, refer to the
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`PTX ISA <https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-instructions-tcgen05-ld>`__.
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'``llvm.nvvm.tcgen05.st.*``'
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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.. code-block:: llvm
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declare void @llvm.nvvm.tcgen05.st.<shape>.<num>(ptr addrspace(6) %tmem_addr, <n x i32> %args, i1 %unpack)
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declare void @llvm.nvvm.tcgen05.st.16x32bx2.<num>(ptr addrspace(6) %tmem_addr, <n x i32> %args, i64 %offset, i1 %unpack)
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Overview:
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"""""""""
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This group of intrinsics asynchronously store data from the source vector into the Tensor Memory at the location
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specified by the 32-bit address operand 'tmem_addr` collectively across all threads of the warps.
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All the threads in the warp must specify the same value of `tmem_addr`, which must be the base address of the
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collective load operation. Otherwise, the behavior is undefined.
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The `shape` qualifier and the `num` qualifier together determines the total dimension of the data ('n') which
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is loaded from the Tensor Memory. The `shape` qualifier indicates the base dimension of data. The `num` qualifier
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indicates the repeat factor on the base dimension resulting in the total dimension of the data that is accessed.
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Allowed values for the 'num' are `x1, x2, x4, x8, x16, x32, x64, x128`.
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Allowed values for the 'shape' in the first intrinsic are `16x64b, 16x128b, 16x256b, 32x32b`.
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Allowed value for the 'shape' in the second intrinsic is `16x32bx2`.
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`args` argument is a vector consisting of one or more 32-bit registers derived from `shape` and
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`num` as listed in the table listed in the `tcgen05.ld` section.
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Each shape support an `unpack` mode to allow a 32-bit element in the register to be unpacked into two 16-bit elements and store them in adjacent columns. `unpack` mode can be enabled by setting the `%unpack` operand to 1 and can be disabled by setting it to 0.
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The last argument `i1 %unpack` is a compile-time constant which when set, indicates that a 32-bit element in the register to be unpacked into two 16-bit elements and store them in adjacent columns.
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For more information, refer to the
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`PTX ISA <https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-instructions-tcgen05-st>`__.
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Other Intrinsics
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----------------
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‎llvm/include/llvm/IR/Intrinsics.td

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@@ -564,6 +564,7 @@ def llvm_v8i32_ty : LLVMType<v8i32>; // 8 x i32
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def llvm_v16i32_ty : LLVMType<v16i32>; // 16 x i32
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def llvm_v32i32_ty : LLVMType<v32i32>; // 32 x i32
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def llvm_v64i32_ty : LLVMType<v64i32>; // 64 x i32
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def llvm_v128i32_ty : LLVMType<v128i32>; //128 x i32
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def llvm_v256i32_ty : LLVMType<v256i32>; //256 x i32
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def llvm_v1i64_ty : LLVMType<v1i64>; // 1 x i64

‎llvm/include/llvm/IR/IntrinsicsNVVM.td

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@@ -656,6 +656,35 @@ class CP_ASYNC_BULK_TENSOR_REDUCE_INTR<int dim, string mode, string op> {
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ImmArg<ArgIndex<FlagsStartIdx>>];
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}
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class NVVM_TCGEN05_LDST_NAME<string Op, string Shape, int Num> {
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string intr = "llvm.nvvm.tcgen05." # Op
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# "." # Shape
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# "." # "x" # !shl(1, Num);
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string record = !subst(".", "_",
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!subst("llvm.", "int_", intr));
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}
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class NVVM_TCGEN05_LDST_ACCESS_SIZE<string Shape, int Num> {
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int shift = !cond(!eq(Shape, "16x128b"): 1,
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!eq(Shape, "16x256b"): 2,
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true : 0);
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int veclen = !shl(1, !add(Num, shift));
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int valid = !le(veclen, 128);
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LLVMType type = !cond(!eq(veclen, 1): llvm_i32_ty,
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!eq(veclen, 2): llvm_v2i32_ty,
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!eq(veclen, 4): llvm_v4i32_ty,
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!eq(veclen, 8): llvm_v8i32_ty,
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!eq(veclen, 16): llvm_v16i32_ty,
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!eq(veclen, 32): llvm_v32i32_ty,
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!eq(veclen, 64): llvm_v64i32_ty,
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!eq(veclen, 128): llvm_v128i32_ty,
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true : llvm_void_ty);
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}
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let TargetPrefix = "nvvm" in {
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def int_nvvm_prmt : ClangBuiltin<"__nvvm_prmt">,
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DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
@@ -5138,4 +5167,40 @@ def int_nvvm_tcgen05_fence_before_thread_sync : Intrinsic<[], [],
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def int_nvvm_tcgen05_fence_after_thread_sync : Intrinsic<[], [],
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[IntrNoMem, IntrHasSideEffects]>;
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// Tcgen05 ld
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class NVVM_TCGEN05_LD<string Shape, int Num> :
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Intrinsic<[NVVM_TCGEN05_LDST_ACCESS_SIZE<Shape, Num>.type],
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!listconcat([llvm_tmem_ptr_ty],
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!if(!eq(Shape, "16x32bx2"), [llvm_i64_ty], []),
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[llvm_i1_ty]),
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!listconcat([IntrConvergent, IntrArgMemOnly, NoCapture<ArgIndex<0>>],
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!if(!eq(Shape, "16x32bx2"),
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[ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>],
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[ImmArg<ArgIndex<1>>])),
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NVVM_TCGEN05_LDST_NAME<"ld", Shape, Num>.intr>;
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// Tcgen05 st
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class NVVM_TCGEN05_ST<string Shape, int Num> :
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Intrinsic<[],
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!listconcat([llvm_tmem_ptr_ty],
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!if(!eq(Shape, "16x32bx2"), [llvm_i64_ty], []),
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[NVVM_TCGEN05_LDST_ACCESS_SIZE<Shape, Num>.type],
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[llvm_i1_ty]),
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!listconcat([IntrConvergent, IntrArgMemOnly, NoCapture<ArgIndex<0>>],
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!if(!eq(Shape, "16x32bx2"),
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[ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<3>>],
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[ImmArg<ArgIndex<2>>])),
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NVVM_TCGEN05_LDST_NAME<"st", Shape, Num>.intr>;
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foreach shape = ["16x64b", "16x128b", "16x256b", "32x32b", "16x32bx2"] in {
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foreach num = !range(0, 8) in {
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if NVVM_TCGEN05_LDST_ACCESS_SIZE<shape, num>.valid then {
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def NVVM_TCGEN05_LDST_NAME<"ld", shape, num>.record:
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NVVM_TCGEN05_LD<shape, num>;
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def NVVM_TCGEN05_LDST_NAME<"st", shape, num>.record:
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NVVM_TCGEN05_ST<shape, num>;
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}
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}
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}
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} // let TargetPrefix = "nvvm"

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