Skip to content

Commit 56fdfe9

Browse files
chuongg3chuongg3
committed
[AArch64][GlobalISel] Legalize G_VECREDUCE_{MIN/MAX}
Legalizes G_VECREDUCE_{MIN/MAX} and selects instructions for vecreduce_{min/max}
1 parent b002b38 commit 56fdfe9

File tree

5 files changed

+1854
-90
lines changed

5 files changed

+1854
-90
lines changed

‎llvm/lib/Target/AArch64/AArch64InstrGISel.td

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -274,6 +274,11 @@ def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
274274

275275
def : GINodeEquiv<G_PREFETCH, AArch64Prefetch>;
276276

277+
def : GINodeEquiv<G_VECREDUCE_UMIN, vecreduce_umin>;
278+
def : GINodeEquiv<G_VECREDUCE_UMAX, vecreduce_umax>;
279+
def : GINodeEquiv<G_VECREDUCE_SMIN, vecreduce_smin>;
280+
def : GINodeEquiv<G_VECREDUCE_SMAX, vecreduce_smax>;
281+
277282
// These are patterns that we only use for GlobalISel via the importer.
278283
def : Pat<(f32 (fadd (vector_extract (v2f32 FPR64:$Rn), (i64 0)),
279284
(vector_extract (v2f32 FPR64:$Rn), (i64 1)))),

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6702,6 +6702,42 @@ defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", AArch64uminv>;
67026702
def : Pat<(v2i32 (AArch64uminv (v2i32 V64:$Rn))),
67036703
(UMINPv2i32 V64:$Rn, V64:$Rn)>;
67046704

6705+
// For vecreduce_{opc}
6706+
multiclass SIMDAcrossLanesVecReductionIntrinsic<string baseOpc,
6707+
SDPatternOperator opNode> {
6708+
def : Pat<(i8 (opNode (v8i8 FPR64:$Rn))),
6709+
(!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) FPR64:$Rn)>;
6710+
6711+
def : Pat<(i8 (opNode (v16i8 FPR128:$Rn))),
6712+
(!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) FPR128:$Rn)>;
6713+
6714+
def : Pat<(i16 (opNode (v4i16 FPR64:$Rn))),
6715+
(!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) FPR64:$Rn)>;
6716+
6717+
def : Pat<(i16 (opNode (v8i16 FPR128:$Rn))),
6718+
(!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) FPR128:$Rn)>;
6719+
6720+
def : Pat<(i32 (opNode (v4i32 V128:$Rn))),
6721+
(!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn)>;
6722+
6723+
}
6724+
6725+
defm : SIMDAcrossLanesVecReductionIntrinsic<"UMINV", vecreduce_umin>;
6726+
def : Pat<(i32 (vecreduce_umin (v2i32 V64:$Rn))),
6727+
(i32 (EXTRACT_SUBREG (UMINPv2i32 V64:$Rn, V64:$Rn), ssub))>;
6728+
6729+
defm : SIMDAcrossLanesVecReductionIntrinsic<"UMAXV", vecreduce_umax>;
6730+
def : Pat<(i32 (vecreduce_umax (v2i32 V64:$Rn))),
6731+
(i32 (EXTRACT_SUBREG (UMAXPv2i32 V64:$Rn, V64:$Rn), ssub))>;
6732+
6733+
defm : SIMDAcrossLanesVecReductionIntrinsic<"SMINV", vecreduce_smin>;
6734+
def : Pat<(i32 (vecreduce_smin (v2i32 V64:$Rn))),
6735+
(i32 (EXTRACT_SUBREG (SMINPv2i32 V64:$Rn, V64:$Rn), ssub))>;
6736+
6737+
defm : SIMDAcrossLanesVecReductionIntrinsic<"SMAXV", vecreduce_smax>;
6738+
def : Pat<(i32 (vecreduce_smax (v2i32 V64:$Rn))),
6739+
(i32 (EXTRACT_SUBREG (SMAXPv2i32 V64:$Rn, V64:$Rn), ssub))>;
6740+
67056741
multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
67066742
def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
67076743
(i32 (SMOVvi16to32

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -990,6 +990,21 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
990990
.scalarize(1)
991991
.lower();
992992

993+
getActionDefinitionsBuilder(
994+
{G_VECREDUCE_SMIN, G_VECREDUCE_SMAX, G_VECREDUCE_UMIN, G_VECREDUCE_UMAX})
995+
.legalFor({{s8, v8s8},
996+
{s8, v16s8},
997+
{s16, v4s16},
998+
{s16, v8s16},
999+
{s32, v2s32},
1000+
{s32, v4s32}})
1001+
.clampMaxNumElements(1, s64, 2)
1002+
.clampMaxNumElements(1, s32, 4)
1003+
.clampMaxNumElements(1, s16, 8)
1004+
.clampMaxNumElements(1, s8, 16)
1005+
.scalarize(1)
1006+
.lower();
1007+
9931008
getActionDefinitionsBuilder(
9941009
{G_VECREDUCE_OR, G_VECREDUCE_AND, G_VECREDUCE_XOR})
9951010
// Try to break down into smaller vectors as long as they're at least 64

‎llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

Lines changed: 11 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -769,17 +769,20 @@
769769
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
770770
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
771771
# DEBUG-NEXT: G_VECREDUCE_SMAX (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
772-
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
773-
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
772+
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
773+
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
774+
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
774775
# DEBUG-NEXT: G_VECREDUCE_SMIN (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
775-
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
776-
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
776+
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
777+
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
777778
# DEBUG-NEXT: G_VECREDUCE_UMAX (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
778-
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
779-
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
779+
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
780+
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
781+
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
780782
# DEBUG-NEXT: G_VECREDUCE_UMIN (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
781-
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
782-
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
783+
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
784+
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
785+
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
783786
# DEBUG-NEXT: G_SBFX (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
784787
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
785788
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK

0 commit comments

Comments
 (0)