@@ -272,36 +272,52 @@ define i64 @loop_contains_safe_div() #1 {
272
272
; CHECK-NEXT: [[P2:%.*]] = alloca [1024 x i8], align 4
273
273
; CHECK-NEXT: call void @init_mem(ptr [[P1]], i64 1024)
274
274
; CHECK-NEXT: call void @init_mem(ptr [[P2]], i64 1024)
275
+ ; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
276
+ ; CHECK-NEXT: [[TMP12:%.*]] = mul i64 [[TMP11]], 4
275
277
; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
276
278
; CHECK: vector.ph:
279
+ ; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
280
+ ; CHECK-NEXT: [[TMP3:%.*]] = mul i64 [[TMP10]], 4
281
+ ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 64, [[TMP3]]
282
+ ; CHECK-NEXT: [[INDEX1:%.*]] = sub i64 64, [[N_MOD_VF]]
283
+ ; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()
284
+ ; CHECK-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 4
285
+ ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 3, [[INDEX1]]
286
+ ; CHECK-NEXT: [[TMP16:%.*]] = call <vscale x 4 x i64> @llvm.stepvector.nxv4i64()
287
+ ; CHECK-NEXT: [[TMP17:%.*]] = mul <vscale x 4 x i64> [[TMP16]], splat (i64 1)
288
+ ; CHECK-NEXT: [[INDUCTION:%.*]] = add <vscale x 4 x i64> splat (i64 3), [[TMP17]]
289
+ ; CHECK-NEXT: [[TMP9:%.*]] = mul i64 1, [[TMP5]]
290
+ ; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[TMP9]], i64 0
291
+ ; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 4 x i64> [[DOTSPLATINSERT]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
277
292
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
278
293
; CHECK: vector.body:
279
- ; CHECK-NEXT: [[INDEX1 :%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT2:%.*]], [[VECTOR_BODY]] ]
280
- ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 3, i64 4> , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
281
- ; CHECK-NEXT: [[OFFSET_IDX :%.*]] = add i64 3, [[INDEX1 ]]
282
- ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX ]], 0
294
+ ; CHECK-NEXT: [[INDEX2 :%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT2:%.*]], [[VECTOR_BODY]] ]
295
+ ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 4 x i64> [ [[INDUCTION]] , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
296
+ ; CHECK-NEXT: [[OFFSET_IDX1 :%.*]] = add i64 3, [[INDEX2 ]]
297
+ ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX1 ]], 0
283
298
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[P1]], i64 [[TMP0]]
284
299
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
285
- ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP2]], align 1
286
- ; CHECK-NEXT: [[TMP3 :%.*]] = udiv <2 x i32> [[WIDE_LOAD]], splat (i32 20000)
287
- ; CHECK-NEXT: [[TMP4 :%.*]] = icmp eq <2 x i32> [[TMP3 ]], splat (i32 1)
288
- ; CHECK-NEXT: [[INDEX_NEXT2]] = add nuw i64 [[INDEX1 ]], 2
289
- ; CHECK-NEXT: [[TMP5 :%.*]] = xor <2 x i1> [[TMP4 ]], splat (i1 true)
290
- ; CHECK-NEXT: [[TMP6:%.*]] = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> [[TMP5 ]])
291
- ; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT2]], 64
292
- ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[VEC_IND]], splat (i64 2)
300
+ ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP2]], align 1
301
+ ; CHECK-NEXT: [[TMP13 :%.*]] = udiv <vscale x 4 x i32> [[WIDE_LOAD]], splat (i32 20000)
302
+ ; CHECK-NEXT: [[TMP14 :%.*]] = icmp eq <vscale x 4 x i32> [[TMP13 ]], splat (i32 1)
303
+ ; CHECK-NEXT: [[INDEX_NEXT2]] = add nuw i64 [[INDEX2 ]], [[TMP5]]
304
+ ; CHECK-NEXT: [[TMP15 :%.*]] = xor <vscale x 4 x i1> [[TMP14 ]], splat (i1 true)
305
+ ; CHECK-NEXT: [[TMP6:%.*]] = call i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1> [[TMP15 ]])
306
+ ; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT2]], [[INDEX1]]
307
+ ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 4 x i64> [[VEC_IND]], [[DOTSPLAT]]
293
308
; CHECK-NEXT: [[TMP8:%.*]] = or i1 [[TMP6]], [[TMP7]]
294
309
; CHECK-NEXT: br i1 [[TMP8]], label [[MIDDLE_SPLIT:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
295
310
; CHECK: middle.split:
296
311
; CHECK-NEXT: br i1 [[TMP6]], label [[VECTOR_EARLY_EXIT:%.*]], label [[MIDDLE_BLOCK:%.*]]
297
312
; CHECK: vector.early.exit:
298
- ; CHECK-NEXT: [[FIRST_ACTIVE_LANE:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v2i1(<2 x i1> [[TMP5 ]], i1 true)
299
- ; CHECK-NEXT: [[EARLY_EXIT_VALUE:%.*]] = extractelement <2 x i64> [[VEC_IND]], i64 [[FIRST_ACTIVE_LANE]]
313
+ ; CHECK-NEXT: [[FIRST_ACTIVE_LANE:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1(<vscale x 4 x i1> [[TMP15 ]], i1 true)
314
+ ; CHECK-NEXT: [[EARLY_EXIT_VALUE:%.*]] = extractelement <vscale x 4 x i64> [[VEC_IND]], i64 [[FIRST_ACTIVE_LANE]]
300
315
; CHECK-NEXT: br label [[LOOP_END:%.*]]
301
316
; CHECK: middle.block:
302
- ; CHECK-NEXT: br i1 true, label [[LOOP_END]], label [[SCALAR_PH]]
317
+ ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 64, [[INDEX1]]
318
+ ; CHECK-NEXT: br i1 [[CMP_N]], label [[LOOP_END]], label [[SCALAR_PH]]
303
319
; CHECK: scalar.ph:
304
- ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 67 , [[MIDDLE_BLOCK]] ], [ 3, [[ENTRY:%.*]] ]
320
+ ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[OFFSET_IDX]] , [[MIDDLE_BLOCK]] ], [ 3, [[ENTRY:%.*]] ]
305
321
; CHECK-NEXT: br label [[LOOP:%.*]]
306
322
; CHECK: loop:
307
323
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ [[INDEX_NEXT:%.*]], [[LOOP_INC:%.*]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
0 commit comments