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Support addrspacecast initializers with isNoopAddrSpaceCast
Moves isNoopAddrSpaceCast to the TargetMachine. It logically belongs with the DataLayout.
1 parent 6983cf3 commit 57bd64f

30 files changed

+131
-78
lines changed

‎llvm/include/llvm/CodeGen/BasicTTIImpl.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -222,7 +222,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
222222
}
223223

224224
bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const {
225-
return getTLI()->isNoopAddrSpaceCast(FromAS, ToAS);
225+
return getTLI()->getTargetMachine().isNoopAddrSpaceCast(FromAS, ToAS);
226226
}
227227

228228
Value *rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV,

‎llvm/include/llvm/CodeGen/TargetLowering.h

Lines changed: 1 addition & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1759,17 +1759,10 @@ class TargetLoweringBase {
17591759
return "";
17601760
}
17611761

1762-
/// Returns true if a cast between SrcAS and DestAS is a noop.
1763-
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1764-
return false;
1765-
}
1766-
17671762
/// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
17681763
/// are happy to sink it into basic blocks. A cast may be free, but not
17691764
/// necessarily a no-op. e.g. a free truncate from a 64-bit to 32-bit pointer.
1770-
virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1771-
return isNoopAddrSpaceCast(SrcAS, DestAS);
1772-
}
1765+
virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const;
17731766

17741767
/// Return true if the pointer arguments to CI should be aligned by aligning
17751768
/// the object whose address is being passed. If so then MinSize is set to the

‎llvm/include/llvm/Target/TargetMachine.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -271,6 +271,11 @@ class TargetMachine {
271271
return Options.BBSectionsFuncListBuf.get();
272272
}
273273

274+
/// Returns true if a cast between SrcAS and DestAS is a noop.
275+
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
276+
return false;
277+
}
278+
274279
/// Get a \c TargetIRAnalysis appropriate for the target.
275280
///
276281
/// This is used to construct the new pass manager's target IR analysis pass,

‎llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2295,6 +2295,16 @@ const MCExpr *AsmPrinter::lowerConstant(const Constant *CV) {
22952295
}
22962296

22972297
switch (CE->getOpcode()) {
2298+
case Instruction::AddrSpaceCast: {
2299+
const Constant *Op = CE->getOperand(0);
2300+
unsigned DstAS = CE->getType()->getPointerAddressSpace();
2301+
unsigned SrcAS = Op->getType()->getPointerAddressSpace();
2302+
if (TM.isNoopAddrSpaceCast(SrcAS, DstAS))
2303+
return lowerConstant(Op);
2304+
2305+
// Fallthrough to error.
2306+
LLVM_FALLTHROUGH;
2307+
}
22982308
default: {
22992309
// If the code isn't optimized, there may be outstanding folding
23002310
// opportunities. Attempt to fold the expression using DataLayout as a

‎llvm/lib/CodeGen/CodeGenPrepare.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4322,7 +4322,7 @@ bool AddressingModeMatcher::matchOperationAddr(User *AddrInst, unsigned Opcode,
43224322
unsigned SrcAS
43234323
= AddrInst->getOperand(0)->getType()->getPointerAddressSpace();
43244324
unsigned DestAS = AddrInst->getType()->getPointerAddressSpace();
4325-
if (TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
4325+
if (TLI.getTargetMachine().isNoopAddrSpaceCast(SrcAS, DestAS))
43264326
return matchAddr(AddrInst->getOperand(0), Depth);
43274327
return false;
43284328
}

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6394,7 +6394,7 @@ static void checkAddrSpaceIsValidForLibcall(const TargetLowering *TLI,
63946394
unsigned AS) {
63956395
// Lowering memcpy / memset / memmove intrinsics to calls is only valid if all
63966396
// pointer operands can be losslessly bitcasted to pointers of address space 0
6397-
if (AS != 0 && !TLI->isNoopAddrSpaceCast(AS, 0)) {
6397+
if (AS != 0 && !TLI->getTargetMachine().isNoopAddrSpaceCast(AS, 0)) {
63986398
report_fatal_error("cannot lower memory intrinsic in address space " +
63996399
Twine(AS));
64006400
}

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3425,7 +3425,7 @@ void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
34253425
unsigned SrcAS = SV->getType()->getPointerAddressSpace();
34263426
unsigned DestAS = I.getType()->getPointerAddressSpace();
34273427

3428-
if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3428+
if (!TM.isNoopAddrSpaceCast(SrcAS, DestAS))
34293429
N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
34303430

34313431
setValue(&I, N);

‎llvm/lib/CodeGen/TargetLoweringBase.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -801,6 +801,11 @@ bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
801801
}
802802
}
803803

804+
bool TargetLoweringBase::isFreeAddrSpaceCast(unsigned SrcAS,
805+
unsigned DestAS) const {
806+
return TM.isNoopAddrSpaceCast(SrcAS, DestAS);
807+
}
808+
804809
void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) {
805810
// If the command-line option was specified, ignore this request.
806811
if (!JumpIsExpensiveOverride.getNumOccurrences())

‎llvm/lib/Target/AArch64/AArch64ISelLowering.h

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -462,12 +462,6 @@ class AArch64TargetLowering : public TargetLowering {
462462

463463
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
464464

465-
/// Returns true if a cast between SrcAS and DestAS is a noop.
466-
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
467-
// Addrspacecasts are always noops.
468-
return true;
469-
}
470-
471465
/// This method returns a target specific FastISel object, or null if the
472466
/// target does not support "fast" ISel.
473467
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,

‎llvm/lib/Target/AArch64/AArch64TargetMachine.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,12 @@ class AArch64TargetMachine : public LLVMTargetMachine {
5757
SMDiagnostic &Error,
5858
SMRange &SourceRange) const override;
5959

60+
/// Returns true if a cast between SrcAS and DestAS is a noop.
61+
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
62+
// Addrspacecasts are always noops.
63+
return true;
64+
}
65+
6066
private:
6167
bool isLittle;
6268
};

‎llvm/lib/Target/AMDGPU/AMDGPU.h

Lines changed: 13 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -281,8 +281,6 @@ enum TargetIndex {
281281
};
282282
}
283283

284-
} // End namespace llvm
285-
286284
/// OpenCL uses address spaces to differentiate between
287285
/// various memory regions on the hardware. On the CPU
288286
/// all of the address spaces point to the same memory,
@@ -339,4 +337,17 @@ namespace AMDGPUAS {
339337
};
340338
}
341339

340+
namespace AMDGPU {
341+
342+
// FIXME: Missing constant_32bit
343+
inline bool isFlatGlobalAddrSpace(unsigned AS) {
344+
return AS == AMDGPUAS::GLOBAL_ADDRESS ||
345+
AS == AMDGPUAS::FLAT_ADDRESS ||
346+
AS == AMDGPUAS::CONSTANT_ADDRESS ||
347+
AS > AMDGPUAS::MAX_AMDGPU_ADDRESS;
348+
}
349+
}
350+
351+
} // End namespace llvm
352+
342353
#endif

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1677,8 +1677,7 @@ bool AMDGPULegalizerInfo::legalizeAddrSpaceCast(
16771677
const AMDGPUTargetMachine &TM
16781678
= static_cast<const AMDGPUTargetMachine &>(MF.getTarget());
16791679

1680-
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1681-
if (ST.getTargetLowering()->isNoopAddrSpaceCast(SrcAS, DestAS)) {
1680+
if (TM.isNoopAddrSpaceCast(SrcAS, DestAS)) {
16821681
MI.setDesc(B.getTII().get(TargetOpcode::G_BITCAST));
16831682
return true;
16841683
}
@@ -2251,8 +2250,7 @@ bool AMDGPULegalizerInfo::legalizeAtomicCmpXChg(
22512250
Register CmpVal = MI.getOperand(2).getReg();
22522251
Register NewVal = MI.getOperand(3).getReg();
22532252

2254-
assert(SITargetLowering::isFlatGlobalAddrSpace(
2255-
MRI.getType(PtrReg).getAddressSpace()) &&
2253+
assert(AMDGPU::isFlatGlobalAddrSpace(MRI.getType(PtrReg).getAddressSpace()) &&
22562254
"this should not have been custom lowered");
22572255

22582256
LLT ValTy = MRI.getType(CmpVal);

‎llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3232,7 +3232,7 @@ AMDGPURegisterBankInfo::getValueMappingForPtr(const MachineRegisterInfo &MRI,
32323232
LLT PtrTy = MRI.getType(PtrReg);
32333233
unsigned Size = PtrTy.getSizeInBits();
32343234
if (Subtarget.useFlatForGlobal() ||
3235-
!SITargetLowering::isFlatGlobalAddrSpace(PtrTy.getAddressSpace()))
3235+
!AMDGPU::isFlatGlobalAddrSpace(PtrTy.getAddressSpace()))
32363236
return AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
32373237

32383238
// If we're using MUBUF instructions for global memory, an SGPR base register
@@ -3258,8 +3258,7 @@ AMDGPURegisterBankInfo::getInstrMappingForLoad(const MachineInstr &MI) const {
32583258

32593259
const RegisterBank *PtrBank = getRegBank(PtrReg, MRI, *TRI);
32603260

3261-
if (PtrBank == &AMDGPU::SGPRRegBank &&
3262-
SITargetLowering::isFlatGlobalAddrSpace(AS)) {
3261+
if (PtrBank == &AMDGPU::SGPRRegBank && AMDGPU::isFlatGlobalAddrSpace(AS)) {
32633262
if (isScalarLoadLegal(MI)) {
32643263
// We have a uniform instruction so we want to use an SMRD load
32653264
ValMapping = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);

‎llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -526,6 +526,12 @@ const R600Subtarget *R600TargetMachine::getSubtargetImpl(
526526
return I.get();
527527
}
528528

529+
bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
530+
unsigned DestAS) const {
531+
return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
532+
AMDGPU::isFlatGlobalAddrSpace(DestAS);
533+
}
534+
529535
TargetTransformInfo
530536
R600TargetMachine::getTargetTransformInfo(const Function &F) {
531537
return TargetTransformInfo(R600TTIImpl(this, F));

‎llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,8 @@ class AMDGPUTargetMachine : public LLVMTargetMachine {
6262
AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
6363
AddrSpace == AMDGPUAS::REGION_ADDRESS) ? -1 : 0;
6464
}
65+
66+
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
6567
};
6668

6769
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -934,7 +934,10 @@ Value *GCNTTIImpl::rewriteIntrinsicWithAddressSpace(IntrinsicInst *II,
934934
Type *MaskTy = MaskOp->getType();
935935

936936
bool DoTruncate = false;
937-
if (!getTLI()->isNoopAddrSpaceCast(OldAS, NewAS)) {
937+
938+
const GCNTargetMachine &TM =
939+
static_cast<const GCNTargetMachine &>(getTLI()->getTargetMachine());
940+
if (!TM.isNoopAddrSpaceCast(OldAS, NewAS)) {
938941
// All valid 64-bit to 32-bit casts work by chopping off the high
939942
// bits. Any masking only clearing the low bits will also apply in the new
940943
// address space.

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 8 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1478,11 +1478,6 @@ EVT SITargetLowering::getOptimalMemOpType(
14781478
return MVT::Other;
14791479
}
14801480

1481-
bool SITargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1482-
unsigned DestAS) const {
1483-
return isFlatGlobalAddrSpace(SrcAS) && isFlatGlobalAddrSpace(DestAS);
1484-
}
1485-
14861481
bool SITargetLowering::isMemOpHasNoClobberedMemOperand(const SDNode *N) const {
14871482
const MemSDNode *MemNode = cast<MemSDNode>(N);
14881483
const Value *Ptr = MemNode->getMemOperand()->getValue();
@@ -1497,7 +1492,9 @@ bool SITargetLowering::isFreeAddrSpaceCast(unsigned SrcAS,
14971492
if (SrcAS == AMDGPUAS::FLAT_ADDRESS)
14981493
return true;
14991494

1500-
return isNoopAddrSpaceCast(SrcAS, DestAS);
1495+
const GCNTargetMachine &TM =
1496+
static_cast<const GCNTargetMachine &>(getTargetMachine());
1497+
return TM.isNoopAddrSpaceCast(SrcAS, DestAS);
15011498
}
15021499

15031500
bool SITargetLowering::isMemOpUniform(const SDNode *N) const {
@@ -2285,8 +2282,10 @@ SDValue SITargetLowering::LowerFormalArguments(
22852282
if (Arg.Flags.isByRef()) {
22862283
SDValue Ptr = lowerKernArgParameterPtr(DAG, DL, Chain, Offset);
22872284

2288-
if (!isNoopAddrSpaceCast(AMDGPUAS::CONSTANT_ADDRESS,
2289-
Arg.Flags.getPointerAddrSpace())) {
2285+
const GCNTargetMachine &TM =
2286+
static_cast<const GCNTargetMachine &>(getTargetMachine());
2287+
if (!TM.isNoopAddrSpaceCast(AMDGPUAS::CONSTANT_ADDRESS,
2288+
Arg.Flags.getPointerAddrSpace())) {
22902289
Ptr = DAG.getAddrSpaceCast(DL, VT, Ptr, AMDGPUAS::CONSTANT_ADDRESS,
22912290
Arg.Flags.getPointerAddrSpace());
22922291
}
@@ -8506,7 +8505,7 @@ SDValue SITargetLowering::LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) co
85068505
unsigned AS = AtomicNode->getAddressSpace();
85078506

85088507
// No custom lowering required for local address space
8509-
if (!isFlatGlobalAddrSpace(AS))
8508+
if (!AMDGPU::isFlatGlobalAddrSpace(AS))
85108509
return Op;
85118510

85128511
// Non-local address space requires custom lowering for atomic compare

‎llvm/lib/Target/AMDGPU/SIISelLowering.h

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -275,15 +275,6 @@ class SITargetLowering final : public AMDGPUTargetLowering {
275275
AS == AMDGPUAS::PRIVATE_ADDRESS;
276276
}
277277

278-
// FIXME: Missing constant_32bit
279-
static bool isFlatGlobalAddrSpace(unsigned AS) {
280-
return AS == AMDGPUAS::GLOBAL_ADDRESS ||
281-
AS == AMDGPUAS::FLAT_ADDRESS ||
282-
AS == AMDGPUAS::CONSTANT_ADDRESS ||
283-
AS > AMDGPUAS::MAX_AMDGPU_ADDRESS;
284-
}
285-
286-
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
287278
bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
288279

289280
TargetLoweringBase::LegalizeTypeAction

‎llvm/lib/Target/ARM/ARMISelLowering.h

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -528,12 +528,6 @@ class VectorType;
528528
const TargetRegisterClass *
529529
getRegClassFor(MVT VT, bool isDivergent = false) const override;
530530

531-
/// Returns true if a cast between SrcAS and DestAS is a noop.
532-
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
533-
// Addrspacecasts are always noops.
534-
return true;
535-
}
536-
537531
bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
538532
unsigned &PrefAlign) const override;
539533

‎llvm/lib/Target/ARM/ARMTargetMachine.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -72,6 +72,12 @@ class ARMBaseTargetMachine : public LLVMTargetMachine {
7272
}
7373

7474
bool targetSchedulesPostRAScheduling() const override { return true; };
75+
76+
/// Returns true if a cast between SrcAS and DestAS is a noop.
77+
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
78+
// Addrspacecasts are always noops.
79+
return true;
80+
}
7581
};
7682

7783
/// ARM/Thumb little endian target machine.

‎llvm/lib/Target/Mips/MipsISelLowering.h

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -365,14 +365,6 @@ class TargetRegisterClass;
365365
return ABI.IsN64() ? Mips::A1_64 : Mips::A1;
366366
}
367367

368-
/// Returns true if a cast between SrcAS and DestAS is a noop.
369-
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
370-
// Mips doesn't have any special address spaces so we just reserve
371-
// the first 256 for software use (e.g. OpenCL) and treat casts
372-
// between them as noops.
373-
return SrcAS < 256 && DestAS < 256;
374-
}
375-
376368
bool isJumpTableRelative() const override {
377369
return getTargetMachine().isPositionIndependent();
378370
}

‎llvm/lib/Target/Mips/MipsTargetMachine.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,14 @@ class MipsTargetMachine : public LLVMTargetMachine {
6363
return TLOF.get();
6464
}
6565

66+
/// Returns true if a cast between SrcAS and DestAS is a noop.
67+
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
68+
// Mips doesn't have any special address spaces so we just reserve
69+
// the first 256 for software use (e.g. OpenCL) and treat casts
70+
// between them as noops.
71+
return SrcAS < 256 && DestAS < 256;
72+
}
73+
6674
bool isLittleEndian() const { return isLittle; }
6775
const MipsABIInfo &getABI() const { return ABI; }
6876
};

‎llvm/lib/Target/PowerPC/PPCISelLowering.h

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1022,11 +1022,6 @@ namespace llvm {
10221022
}
10231023
};
10241024

1025-
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
1026-
// Addrspacecasts are always noops.
1027-
return true;
1028-
}
1029-
10301025
bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
10311026
SelectionDAG &DAG,
10321027
ISD::LoadExtType ET = ISD::NON_EXTLOAD) const;

‎llvm/lib/Target/PowerPC/PPCTargetMachine.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,11 @@ class PPCTargetMachine final : public LLVMTargetMachine {
5858
const Triple &TT = getTargetTriple();
5959
return (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le);
6060
};
61+
62+
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
63+
// Addrspacecasts are always noops.
64+
return true;
65+
}
6166
};
6267
} // end namespace llvm
6368

‎llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -2537,17 +2537,6 @@ Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
25372537
return TargetLowering::getSafeStackPointerLocation(IRB);
25382538
}
25392539

2540-
bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2541-
unsigned DestAS) const {
2542-
assert(SrcAS != DestAS && "Expected different address spaces!");
2543-
2544-
const TargetMachine &TM = getTargetMachine();
2545-
if (TM.getPointerSize(SrcAS) != TM.getPointerSize(DestAS))
2546-
return false;
2547-
2548-
return SrcAS < 256 && DestAS < 256;
2549-
}
2550-
25512540
//===----------------------------------------------------------------------===//
25522541
// Return Value Calling Convention Implementation
25532542
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/X86/X86ISelLowering.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1349,8 +1349,6 @@ namespace llvm {
13491349
Align Alignment,
13501350
SelectionDAG &DAG) const;
13511351

1352-
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
1353-
13541352
/// Customize the preferred legalization strategy for certain types.
13551353
LegalizeTypeAction getPreferredVectorAction(MVT VT) const override;
13561354

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