Skip to content

Commit 5889f68

Browse files
V-FEXrtV-FEXrt
authored
[NFC][SPIRV] Cleanup selectOpWithSrc functions (#117077)
As a follow up request from #111082 (comment) the following non functional changes have been make - `selectNAryOpWithSrcs` has been renamed to `selectOpWithSrcs` - Calls to `selectUnOpWithSrc` have been replaced with `selectOpWithSrcs` - `selectUnOpWithSrc` has been deleted
1 parent 5d32a14 commit 5889f68

File tree

1 file changed

+23
-39
lines changed

1 file changed

+23
-39
lines changed

‎llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

Lines changed: 23 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -109,13 +109,10 @@ class SPIRVInstructionSelector : public InstructionSelector {
109109
bool selectGlobalValue(Register ResVReg, MachineInstr &I,
110110
const MachineInstr *Init = nullptr) const;
111111

112-
bool selectNAryOpWithSrcs(Register ResVReg, const SPIRVType *ResType,
113-
MachineInstr &I, std::vector<Register> SrcRegs,
114-
unsigned Opcode) const;
112+
bool selectOpWithSrcs(Register ResVReg, const SPIRVType *ResType,
113+
MachineInstr &I, std::vector<Register> SrcRegs,
114+
unsigned Opcode) const;
115115

116-
bool selectUnOpWithSrc(Register ResVReg, const SPIRVType *ResType,
117-
MachineInstr &I, Register SrcReg,
118-
unsigned Opcode) const;
119116
bool selectUnOp(Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
120117
unsigned Opcode) const;
121118

@@ -859,11 +856,11 @@ bool SPIRVInstructionSelector::selectExtInst(Register ResVReg,
859856
return false;
860857
}
861858

862-
bool SPIRVInstructionSelector::selectNAryOpWithSrcs(Register ResVReg,
863-
const SPIRVType *ResType,
864-
MachineInstr &I,
865-
std::vector<Register> Srcs,
866-
unsigned Opcode) const {
859+
bool SPIRVInstructionSelector::selectOpWithSrcs(Register ResVReg,
860+
const SPIRVType *ResType,
861+
MachineInstr &I,
862+
std::vector<Register> Srcs,
863+
unsigned Opcode) const {
867864
auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode))
868865
.addDef(ResVReg)
869866
.addUse(GR.getSPIRVTypeID(ResType));
@@ -873,18 +870,6 @@ bool SPIRVInstructionSelector::selectNAryOpWithSrcs(Register ResVReg,
873870
return MIB.constrainAllUses(TII, TRI, RBI);
874871
}
875872

876-
bool SPIRVInstructionSelector::selectUnOpWithSrc(Register ResVReg,
877-
const SPIRVType *ResType,
878-
MachineInstr &I,
879-
Register SrcReg,
880-
unsigned Opcode) const {
881-
return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode))
882-
.addDef(ResVReg)
883-
.addUse(GR.getSPIRVTypeID(ResType))
884-
.addUse(SrcReg)
885-
.constrainAllUses(TII, TRI, RBI);
886-
}
887-
888873
bool SPIRVInstructionSelector::selectUnOp(Register ResVReg,
889874
const SPIRVType *ResType,
890875
MachineInstr &I,
@@ -920,8 +905,8 @@ bool SPIRVInstructionSelector::selectUnOp(Register ResVReg,
920905
.constrainAllUses(TII, TRI, RBI);
921906
}
922907
}
923-
return selectUnOpWithSrc(ResVReg, ResType, I, I.getOperand(1).getReg(),
924-
Opcode);
908+
return selectOpWithSrcs(ResVReg, ResType, I, {I.getOperand(1).getReg()},
909+
Opcode);
925910
}
926911

927912
bool SPIRVInstructionSelector::selectBitcast(Register ResVReg,
@@ -1066,7 +1051,7 @@ bool SPIRVInstructionSelector::selectMemOperation(Register ResVReg,
10661051
SPIRVType *SourceTy = GR.getOrCreateSPIRVPointerType(
10671052
ValTy, I, TII, SPIRV::StorageClass::UniformConstant);
10681053
SrcReg = MRI->createGenericVirtualRegister(LLT::scalar(64));
1069-
selectUnOpWithSrc(SrcReg, SourceTy, I, VarReg, SPIRV::OpBitcast);
1054+
selectOpWithSrcs(SrcReg, SourceTy, I, {VarReg}, SPIRV::OpBitcast);
10701055
}
10711056
auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCopyMemorySized))
10721057
.addUse(I.getOperand(0).getReg())
@@ -1111,7 +1096,7 @@ bool SPIRVInstructionSelector::selectAtomicRMW(Register ResVReg,
11111096
if (NegateOpcode != 0) {
11121097
// Translation with negative value operand is requested
11131098
Register TmpReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
1114-
Result &= selectUnOpWithSrc(TmpReg, ResType, I, ValueReg, NegateOpcode);
1099+
Result &= selectOpWithSrcs(TmpReg, ResType, I, {ValueReg}, NegateOpcode);
11151100
ValueReg = TmpReg;
11161101
}
11171102

@@ -2374,7 +2359,7 @@ bool SPIRVInstructionSelector::selectIToF(Register ResVReg,
23742359
SrcReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
23752360
selectSelect(SrcReg, TmpType, I, false);
23762361
}
2377-
return selectUnOpWithSrc(ResVReg, ResType, I, SrcReg, Opcode);
2362+
return selectOpWithSrcs(ResVReg, ResType, I, {SrcReg}, Opcode);
23782363
}
23792364

23802365
bool SPIRVInstructionSelector::selectExt(Register ResVReg,
@@ -3068,7 +3053,7 @@ bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
30683053
// zero or sign extend
30693054
Register ExtReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
30703055
bool Result =
3071-
selectUnOpWithSrc(ExtReg, ResType, I, I.getOperand(2).getReg(), Opcode);
3056+
selectOpWithSrcs(ExtReg, ResType, I, {I.getOperand(2).getReg()}, Opcode);
30723057
return Result && selectFirstBitHigh32(ResVReg, ResType, I, ExtReg, IsSigned);
30733058
}
30743059

@@ -3100,7 +3085,7 @@ bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
31003085
GR.getOrCreateSPIRVVectorType(baseType, 2 * count, MIRBuilder);
31013086
Register bitcastReg = MRI->createVirtualRegister(GR.getRegClass(postCastT));
31023087
bool Result =
3103-
selectUnOpWithSrc(bitcastReg, postCastT, I, OpReg, SPIRV::OpBitcast);
3088+
selectOpWithSrcs(bitcastReg, postCastT, I, {OpReg}, SPIRV::OpBitcast);
31043089

31053090
// 2. call firstbithigh
31063091
Register FBHReg = MRI->createVirtualRegister(GR.getRegClass(postCastT));
@@ -3114,11 +3099,11 @@ bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
31143099
bool isScalarRes = ResType->getOpcode() != SPIRV::OpTypeVector;
31153100
if (isScalarRes) {
31163101
// if scalar do a vector extract
3117-
Result &= selectNAryOpWithSrcs(
3102+
Result &= selectOpWithSrcs(
31183103
HighReg, ResType, I,
31193104
{FBHReg, GR.getOrCreateConstInt(0, I, ResType, TII, ZeroAsNull)},
31203105
SPIRV::OpVectorExtractDynamic);
3121-
Result &= selectNAryOpWithSrcs(
3106+
Result &= selectOpWithSrcs(
31223107
LowReg, ResType, I,
31233108
{FBHReg, GR.getOrCreateConstInt(1, I, ResType, TII, ZeroAsNull)},
31243109
SPIRV::OpVectorExtractDynamic);
@@ -3176,21 +3161,20 @@ bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
31763161

31773162
// check if the high bits are == -1; true if -1
31783163
Register BReg = MRI->createVirtualRegister(GR.getRegClass(BoolType));
3179-
Result &= selectNAryOpWithSrcs(BReg, BoolType, I, {HighReg, NegOneReg},
3180-
SPIRV::OpIEqual);
3164+
Result &= selectOpWithSrcs(BReg, BoolType, I, {HighReg, NegOneReg},
3165+
SPIRV::OpIEqual);
31813166

31823167
// Select low bits if true in BReg, otherwise high bits
31833168
Register TmpReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
3184-
Result &= selectNAryOpWithSrcs(TmpReg, ResType, I, {BReg, LowReg, HighReg},
3185-
selectOp);
3169+
Result &=
3170+
selectOpWithSrcs(TmpReg, ResType, I, {BReg, LowReg, HighReg}, selectOp);
31863171

31873172
// Add 32 for high bits, 0 for low bits
31883173
Register ValReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
3189-
Result &=
3190-
selectNAryOpWithSrcs(ValReg, ResType, I, {BReg, Reg0, Reg32}, selectOp);
3174+
Result &= selectOpWithSrcs(ValReg, ResType, I, {BReg, Reg0, Reg32}, selectOp);
31913175

31923176
return Result &&
3193-
selectNAryOpWithSrcs(ResVReg, ResType, I, {ValReg, TmpReg}, addOp);
3177+
selectOpWithSrcs(ResVReg, ResType, I, {ValReg, TmpReg}, addOp);
31943178
}
31953179

31963180
bool SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg,

0 commit comments

Comments
 (0)