Fixups

sdesmalen-arm · sdesmalen-arm · commit 588de8521a2c · 2024-11-01T12:10:26.000Z
diff --git a/llvm/test/TableGen/ArtificialSubregs.td b/llvm/test/TableGen/ArtificialSubregs.td
@@ -16,7 +16,7 @@ include "llvm/Target/Target.td"
 //                 \      /
 //                   qsub
 //
-// Where the _hi parts are artificial and where ubregs ssub, dsub and qsub
+// Where the _hi parts are artificial and where subregs ssub, dsub and qsub
 // are all addressable as real registers.
 //
 // These are then used in {S0, S1, S2}, {D0, D1, D2} and {Q0, Q1, Q2},
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -410,7 +410,7 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
         Parts.push_back(getSubRegIndex(SR->ExplicitSubRegs[j]));
     }
 
-    if (Parts.size() < 2)
+    if (Parts.size() != SR->ExplicitSubRegs.size())
       continue;
 
     // Offer this as an existing spelling for the concatenation of Parts.

Original file line number	Diff line number	Diff line change
`@@ -410,7 +410,7 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {`
`410`	`410`	`Parts.push_back(getSubRegIndex(SR->ExplicitSubRegs[j]));`
`411`	`411`	`}`
`412`	`412`
`413`		`- if (Parts.size() < 2)`
	`413`	`+ if (Parts.size() != SR->ExplicitSubRegs.size())`
`414`	`414`	`continue;`
`415`	`415`
`416`	`416`	`// Offer this as an existing spelling for the concatenation of Parts.`