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[DAGCombiner] Teach scalarizeBinOpOfSplats handle scalable splat.
This revision supports to scalarize a binary operation of two scalable splat vectors. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D122791
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7 files changed

+32
-19
lines changed

7 files changed

+32
-19
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23466,10 +23466,14 @@ static SDValue scalarizeBinOpOfSplats(SDNode *N, SelectionDAG &DAG,
2346623466
int Index0, Index1;
2346723467
SDValue Src0 = DAG.getSplatSourceVector(N0, Index0);
2346823468
SDValue Src1 = DAG.getSplatSourceVector(N1, Index1);
23469+
// Extract element from splat_vector should be free.
23470+
// TODO: use DAG.isSplatValue instead?
23471+
bool IsBothSplatVector = N0.getOpcode() == ISD::SPLAT_VECTOR &&
23472+
N1.getOpcode() == ISD::SPLAT_VECTOR;
2346923473
if (!Src0 || !Src1 || Index0 != Index1 ||
2347023474
Src0.getValueType().getVectorElementType() != EltVT ||
2347123475
Src1.getValueType().getVectorElementType() != EltVT ||
23472-
!TLI.isExtractVecEltCheap(VT, Index0) ||
23476+
!(IsBothSplatVector || TLI.isExtractVecEltCheap(VT, Index0)) ||
2347323477
!TLI.isOperationLegalOrCustom(Opcode, EltVT))
2347423478
return SDValue();
2347523479

@@ -23491,6 +23495,8 @@ static SDValue scalarizeBinOpOfSplats(SDNode *N, SelectionDAG &DAG,
2349123495
}
2349223496

2349323497
// bo (splat X, Index), (splat Y, Index) --> splat (bo X, Y), Index
23498+
if (VT.isScalableVector())
23499+
return DAG.getSplatVector(VT, DL, ScalarBO);
2349423500
SmallVector<SDValue, 8> Ops(VT.getVectorNumElements(), ScalarBO);
2349523501
return DAG.getBuildVector(VT, DL, Ops);
2349623502
}

‎llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -879,9 +879,9 @@ define <vscale x 8 x i64> @vadd_xx_nxv8i64(i64 %a, i64 %b) nounwind {
879879
;
880880
; RV64-LABEL: vadd_xx_nxv8i64:
881881
; RV64: # %bb.0:
882-
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
882+
; RV64-NEXT: add a0, a0, a1
883+
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
883884
; RV64-NEXT: vmv.v.x v8, a0
884-
; RV64-NEXT: vadd.vx v8, v8, a1
885885
; RV64-NEXT: ret
886886
%head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
887887
%splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer

‎llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1370,9 +1370,9 @@ define <vscale x 8 x i64> @vand_xx_nxv8i64(i64 %a, i64 %b) nounwind {
13701370
;
13711371
; RV64-LABEL: vand_xx_nxv8i64:
13721372
; RV64: # %bb.0:
1373-
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
1373+
; RV64-NEXT: and a0, a0, a1
1374+
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
13741375
; RV64-NEXT: vmv.v.x v8, a0
1375-
; RV64-NEXT: vand.vx v8, v8, a1
13761376
; RV64-NEXT: ret
13771377
%head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
13781378
%splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer

‎llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll

Lines changed: 15 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
3-
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
3+
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64NOM
44

55
; RUN: llc -mtriple=riscv32 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
6-
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
6+
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64M
77

88
define <vscale x 1 x i8> @vmul_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
99
; CHECK-LABEL: vmul_vv_nxv1i8:
@@ -939,12 +939,19 @@ define <vscale x 8 x i64> @vmul_xx_nxv8i64(i64 %a, i64 %b) nounwind {
939939
; RV32-NEXT: addi sp, sp, 16
940940
; RV32-NEXT: ret
941941
;
942-
; RV64-LABEL: vmul_xx_nxv8i64:
943-
; RV64: # %bb.0:
944-
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
945-
; RV64-NEXT: vmv.v.x v8, a0
946-
; RV64-NEXT: vmul.vx v8, v8, a1
947-
; RV64-NEXT: ret
942+
; RV64NOM-LABEL: vmul_xx_nxv8i64:
943+
; RV64NOM: # %bb.0:
944+
; RV64NOM-NEXT: vsetvli a2, zero, e64, m8, ta, mu
945+
; RV64NOM-NEXT: vmv.v.x v8, a0
946+
; RV64NOM-NEXT: vmul.vx v8, v8, a1
947+
; RV64NOM-NEXT: ret
948+
;
949+
; RV64M-LABEL: vmul_xx_nxv8i64:
950+
; RV64M: # %bb.0:
951+
; RV64M-NEXT: mul a0, a0, a1
952+
; RV64M-NEXT: vsetvli a1, zero, e64, m8, ta, mu
953+
; RV64M-NEXT: vmv.v.x v8, a0
954+
; RV64M-NEXT: ret
948955
%head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
949956
%splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
950957
%head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0

‎llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1163,9 +1163,9 @@ define <vscale x 8 x i64> @vor_xx_nxv8i64(i64 %a, i64 %b) nounwind {
11631163
;
11641164
; RV64-LABEL: vor_xx_nxv8i64:
11651165
; RV64: # %bb.0:
1166-
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
1166+
; RV64-NEXT: or a0, a0, a1
1167+
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
11671168
; RV64-NEXT: vmv.v.x v8, a0
1168-
; RV64-NEXT: vor.vx v8, v8, a1
11691169
; RV64-NEXT: ret
11701170
%head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
11711171
%splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer

‎llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -857,9 +857,9 @@ define <vscale x 8 x i64> @vsub_xx_nxv8i64(i64 %a, i64 %b) nounwind {
857857
;
858858
; RV64-LABEL: vsub_xx_nxv8i64:
859859
; RV64: # %bb.0:
860-
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
860+
; RV64-NEXT: sub a0, a0, a1
861+
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
861862
; RV64-NEXT: vmv.v.x v8, a0
862-
; RV64-NEXT: vsub.vx v8, v8, a1
863863
; RV64-NEXT: ret
864864
%head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
865865
%splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer

‎llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1370,9 +1370,9 @@ define <vscale x 8 x i64> @vxor_xx_nxv8i64(i64 %a, i64 %b) nounwind {
13701370
;
13711371
; RV64-LABEL: vxor_xx_nxv8i64:
13721372
; RV64: # %bb.0:
1373-
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
1373+
; RV64-NEXT: xor a0, a0, a1
1374+
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
13741375
; RV64-NEXT: vmv.v.x v8, a0
1375-
; RV64-NEXT: vxor.vx v8, v8, a1
13761376
; RV64-NEXT: ret
13771377
%head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
13781378
%splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer

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