Skip to content

Commit 5973272

Browse files
wangpc-ppwangpc-pp
authored
[RISCV] Add MinimumJumpTableEntries to TuneInfo (#72963)
This is like what AArch64 has done in #71166 except that we don't handle `HasMinSize` case now.
1 parent 0d2860b commit 5973272

File tree

6 files changed

+301
-3
lines changed

6 files changed

+301
-3
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1363,8 +1363,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
13631363
setPrefFunctionAlignment(Subtarget.getPrefFunctionAlignment());
13641364
setPrefLoopAlignment(Subtarget.getPrefLoopAlignment());
13651365

1366-
setMinimumJumpTableEntries(5);
1367-
13681366
// Jumps are expensive, compared to logic
13691367
setJumpIsExpensive();
13701368

@@ -19701,6 +19699,11 @@ bool RISCVTargetLowering::shouldFoldSelectWithSingleBitTest(
1970119699
return AndMask.ugt(1024);
1970219700
return TargetLowering::shouldFoldSelectWithSingleBitTest(VT, AndMask);
1970319701
}
19702+
19703+
unsigned RISCVTargetLowering::getMinimumJumpTableEntries() const {
19704+
return Subtarget.getMinimumJumpTableEntries();
19705+
}
19706+
1970419707
namespace llvm::RISCVVIntrinsicsTable {
1970519708

1970619709
#define GET_RISCVVIntrinsicsTable_IMPL

‎llvm/lib/Target/RISCV/RISCVISelLowering.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -962,6 +962,8 @@ class RISCVTargetLowering : public TargetLowering {
962962

963963
bool shouldFoldSelectWithSingleBitTest(EVT VT,
964964
const APInt &AndMask) const override;
965+
966+
unsigned getMinimumJumpTableEntries() const override;
965967
};
966968

967969
namespace RISCV {

‎llvm/lib/Target/RISCV/RISCVProcessors.td

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,14 +19,17 @@ class RISCVTuneInfo {
1919
bits<16> PrefetchDistance = 0;
2020
bits<16> MinPrefetchStride = 1;
2121
bits<32> MaxPrefetchIterationsAhead = -1;
22+
23+
bits<32> MinimumJumpTableEntries = 5;
2224
}
2325

2426
def RISCVTuneInfoTable : GenericTable {
2527
let FilterClass = "RISCVTuneInfo";
2628
let CppTypeName = "RISCVTuneInfo";
2729
let Fields = ["Name", "PrefFunctionAlignment", "PrefLoopAlignment",
2830
"CacheLineSize", "PrefetchDistance",
29-
"MinPrefetchStride", "MaxPrefetchIterationsAhead"];
31+
"MinPrefetchStride", "MaxPrefetchIterationsAhead",
32+
"MinimumJumpTableEntries"];
3033
}
3134

3235
def getRISCVTuneInfo : SearchIndex {

‎llvm/lib/Target/RISCV/RISCVSubtarget.cpp

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,10 @@ static cl::opt<unsigned> RISCVMaxBuildIntsCost(
5757
static cl::opt<bool> UseAA("riscv-use-aa", cl::init(true),
5858
cl::desc("Enable the use of AA during codegen."));
5959

60+
static cl::opt<unsigned> RISCVMinimumJumpTableEntries(
61+
"riscv-min-jump-table-entries", cl::Hidden,
62+
cl::desc("Set minimum number of entries to use a jump table on RISCV"));
63+
6064
void RISCVSubtarget::anchor() {}
6165

6266
RISCVSubtarget &
@@ -189,3 +193,9 @@ void RISCVSubtarget::getPostRAMutations(
189193
/// Enable use of alias analysis during code generation (during MI
190194
/// scheduling, DAGCombine, etc.).
191195
bool RISCVSubtarget::useAA() const { return UseAA; }
196+
197+
unsigned RISCVSubtarget::getMinimumJumpTableEntries() const {
198+
return RISCVMinimumJumpTableEntries.getNumOccurrences() > 0
199+
? RISCVMinimumJumpTableEntries
200+
: TuneInfo->MinimumJumpTableEntries;
201+
}

‎llvm/lib/Target/RISCV/RISCVSubtarget.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,8 @@ struct RISCVTuneInfo {
4444
uint16_t PrefetchDistance;
4545
uint16_t MinPrefetchStride;
4646
unsigned MaxPrefetchIterationsAhead;
47+
48+
unsigned MinimumJumpTableEntries;
4749
};
4850

4951
#define GET_RISCVTuneInfoTable_DECL
@@ -270,6 +272,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
270272
unsigned getMaxPrefetchIterationsAhead() const override {
271273
return TuneInfo->MaxPrefetchIterationsAhead;
272274
};
275+
276+
unsigned getMinimumJumpTableEntries() const;
273277
};
274278
} // End llvm namespace
275279

‎llvm/test/CodeGen/RISCV/jumptable.ll

Lines changed: 276 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,18 @@
1111
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64I-MEDIUM
1212
; RUN: llc -mtriple=riscv64 -relocation-model=pic -verify-machineinstrs < %s \
1313
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64I-PIC
14+
; RUN: llc -mtriple=riscv32 -code-model=small -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
15+
; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I-SMALL-7-ENTRIES
16+
; RUN: llc -mtriple=riscv32 -code-model=medium -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
17+
; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I-MEDIUM-7-ENTRIES
18+
; RUN: llc -mtriple=riscv32 -relocation-model=pic -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
19+
; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I-PIC-7-ENTRIES
20+
; RUN: llc -mtriple=riscv64 -code-model=small -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
21+
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64I-SMALL-7-ENTRIES
22+
; RUN: llc -mtriple=riscv64 -code-model=medium -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
23+
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64I-MEDIUM-7-ENTRIES
24+
; RUN: llc -mtriple=riscv64 -relocation-model=pic -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
25+
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64I-PIC-7-ENTRIES
1426

1527
define void @below_threshold(i32 signext %in, ptr %out) nounwind {
1628
; CHECK-LABEL: below_threshold:
@@ -277,6 +289,270 @@ define void @above_threshold(i32 signext %in, ptr %out) nounwind {
277289
; RV64I-PIC-NEXT: sw a0, 0(a1)
278290
; RV64I-PIC-NEXT: .LBB1_9: # %exit
279291
; RV64I-PIC-NEXT: ret
292+
;
293+
; RV32I-SMALL-7-ENTRIES-LABEL: above_threshold:
294+
; RV32I-SMALL-7-ENTRIES: # %bb.0: # %entry
295+
; RV32I-SMALL-7-ENTRIES-NEXT: li a2, 3
296+
; RV32I-SMALL-7-ENTRIES-NEXT: blt a2, a0, .LBB1_5
297+
; RV32I-SMALL-7-ENTRIES-NEXT: # %bb.1: # %entry
298+
; RV32I-SMALL-7-ENTRIES-NEXT: li a2, 1
299+
; RV32I-SMALL-7-ENTRIES-NEXT: beq a0, a2, .LBB1_9
300+
; RV32I-SMALL-7-ENTRIES-NEXT: # %bb.2: # %entry
301+
; RV32I-SMALL-7-ENTRIES-NEXT: li a2, 2
302+
; RV32I-SMALL-7-ENTRIES-NEXT: beq a0, a2, .LBB1_11
303+
; RV32I-SMALL-7-ENTRIES-NEXT: # %bb.3: # %entry
304+
; RV32I-SMALL-7-ENTRIES-NEXT: li a2, 3
305+
; RV32I-SMALL-7-ENTRIES-NEXT: bne a0, a2, .LBB1_14
306+
; RV32I-SMALL-7-ENTRIES-NEXT: # %bb.4: # %bb3
307+
; RV32I-SMALL-7-ENTRIES-NEXT: li a0, 2
308+
; RV32I-SMALL-7-ENTRIES-NEXT: j .LBB1_13
309+
; RV32I-SMALL-7-ENTRIES-NEXT: .LBB1_5: # %entry
310+
; RV32I-SMALL-7-ENTRIES-NEXT: li a2, 4
311+
; RV32I-SMALL-7-ENTRIES-NEXT: beq a0, a2, .LBB1_10
312+
; RV32I-SMALL-7-ENTRIES-NEXT: # %bb.6: # %entry
313+
; RV32I-SMALL-7-ENTRIES-NEXT: li a2, 5
314+
; RV32I-SMALL-7-ENTRIES-NEXT: beq a0, a2, .LBB1_12
315+
; RV32I-SMALL-7-ENTRIES-NEXT: # %bb.7: # %entry
316+
; RV32I-SMALL-7-ENTRIES-NEXT: li a2, 6
317+
; RV32I-SMALL-7-ENTRIES-NEXT: bne a0, a2, .LBB1_14
318+
; RV32I-SMALL-7-ENTRIES-NEXT: # %bb.8: # %bb6
319+
; RV32I-SMALL-7-ENTRIES-NEXT: li a0, 200
320+
; RV32I-SMALL-7-ENTRIES-NEXT: j .LBB1_13
321+
; RV32I-SMALL-7-ENTRIES-NEXT: .LBB1_9: # %bb1
322+
; RV32I-SMALL-7-ENTRIES-NEXT: li a0, 4
323+
; RV32I-SMALL-7-ENTRIES-NEXT: j .LBB1_13
324+
; RV32I-SMALL-7-ENTRIES-NEXT: .LBB1_10: # %bb4
325+
; RV32I-SMALL-7-ENTRIES-NEXT: li a0, 1
326+
; RV32I-SMALL-7-ENTRIES-NEXT: j .LBB1_13
327+
; RV32I-SMALL-7-ENTRIES-NEXT: .LBB1_11: # %bb2
328+
; RV32I-SMALL-7-ENTRIES-NEXT: li a0, 3
329+
; RV32I-SMALL-7-ENTRIES-NEXT: j .LBB1_13
330+
; RV32I-SMALL-7-ENTRIES-NEXT: .LBB1_12: # %bb5
331+
; RV32I-SMALL-7-ENTRIES-NEXT: li a0, 100
332+
; RV32I-SMALL-7-ENTRIES-NEXT: .LBB1_13: # %exit
333+
; RV32I-SMALL-7-ENTRIES-NEXT: sw a0, 0(a1)
334+
; RV32I-SMALL-7-ENTRIES-NEXT: .LBB1_14: # %exit
335+
; RV32I-SMALL-7-ENTRIES-NEXT: ret
336+
;
337+
; RV32I-MEDIUM-7-ENTRIES-LABEL: above_threshold:
338+
; RV32I-MEDIUM-7-ENTRIES: # %bb.0: # %entry
339+
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a2, 3
340+
; RV32I-MEDIUM-7-ENTRIES-NEXT: blt a2, a0, .LBB1_5
341+
; RV32I-MEDIUM-7-ENTRIES-NEXT: # %bb.1: # %entry
342+
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a2, 1
343+
; RV32I-MEDIUM-7-ENTRIES-NEXT: beq a0, a2, .LBB1_9
344+
; RV32I-MEDIUM-7-ENTRIES-NEXT: # %bb.2: # %entry
345+
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a2, 2
346+
; RV32I-MEDIUM-7-ENTRIES-NEXT: beq a0, a2, .LBB1_11
347+
; RV32I-MEDIUM-7-ENTRIES-NEXT: # %bb.3: # %entry
348+
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a2, 3
349+
; RV32I-MEDIUM-7-ENTRIES-NEXT: bne a0, a2, .LBB1_14
350+
; RV32I-MEDIUM-7-ENTRIES-NEXT: # %bb.4: # %bb3
351+
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a0, 2
352+
; RV32I-MEDIUM-7-ENTRIES-NEXT: j .LBB1_13
353+
; RV32I-MEDIUM-7-ENTRIES-NEXT: .LBB1_5: # %entry
354+
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a2, 4
355+
; RV32I-MEDIUM-7-ENTRIES-NEXT: beq a0, a2, .LBB1_10
356+
; RV32I-MEDIUM-7-ENTRIES-NEXT: # %bb.6: # %entry
357+
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a2, 5
358+
; RV32I-MEDIUM-7-ENTRIES-NEXT: beq a0, a2, .LBB1_12
359+
; RV32I-MEDIUM-7-ENTRIES-NEXT: # %bb.7: # %entry
360+
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a2, 6
361+
; RV32I-MEDIUM-7-ENTRIES-NEXT: bne a0, a2, .LBB1_14
362+
; RV32I-MEDIUM-7-ENTRIES-NEXT: # %bb.8: # %bb6
363+
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a0, 200
364+
; RV32I-MEDIUM-7-ENTRIES-NEXT: j .LBB1_13
365+
; RV32I-MEDIUM-7-ENTRIES-NEXT: .LBB1_9: # %bb1
366+
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a0, 4
367+
; RV32I-MEDIUM-7-ENTRIES-NEXT: j .LBB1_13
368+
; RV32I-MEDIUM-7-ENTRIES-NEXT: .LBB1_10: # %bb4
369+
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a0, 1
370+
; RV32I-MEDIUM-7-ENTRIES-NEXT: j .LBB1_13
371+
; RV32I-MEDIUM-7-ENTRIES-NEXT: .LBB1_11: # %bb2
372+
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a0, 3
373+
; RV32I-MEDIUM-7-ENTRIES-NEXT: j .LBB1_13
374+
; RV32I-MEDIUM-7-ENTRIES-NEXT: .LBB1_12: # %bb5
375+
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a0, 100
376+
; RV32I-MEDIUM-7-ENTRIES-NEXT: .LBB1_13: # %exit
377+
; RV32I-MEDIUM-7-ENTRIES-NEXT: sw a0, 0(a1)
378+
; RV32I-MEDIUM-7-ENTRIES-NEXT: .LBB1_14: # %exit
379+
; RV32I-MEDIUM-7-ENTRIES-NEXT: ret
380+
;
381+
; RV32I-PIC-7-ENTRIES-LABEL: above_threshold:
382+
; RV32I-PIC-7-ENTRIES: # %bb.0: # %entry
383+
; RV32I-PIC-7-ENTRIES-NEXT: li a2, 3
384+
; RV32I-PIC-7-ENTRIES-NEXT: blt a2, a0, .LBB1_5
385+
; RV32I-PIC-7-ENTRIES-NEXT: # %bb.1: # %entry
386+
; RV32I-PIC-7-ENTRIES-NEXT: li a2, 1
387+
; RV32I-PIC-7-ENTRIES-NEXT: beq a0, a2, .LBB1_9
388+
; RV32I-PIC-7-ENTRIES-NEXT: # %bb.2: # %entry
389+
; RV32I-PIC-7-ENTRIES-NEXT: li a2, 2
390+
; RV32I-PIC-7-ENTRIES-NEXT: beq a0, a2, .LBB1_11
391+
; RV32I-PIC-7-ENTRIES-NEXT: # %bb.3: # %entry
392+
; RV32I-PIC-7-ENTRIES-NEXT: li a2, 3
393+
; RV32I-PIC-7-ENTRIES-NEXT: bne a0, a2, .LBB1_14
394+
; RV32I-PIC-7-ENTRIES-NEXT: # %bb.4: # %bb3
395+
; RV32I-PIC-7-ENTRIES-NEXT: li a0, 2
396+
; RV32I-PIC-7-ENTRIES-NEXT: j .LBB1_13
397+
; RV32I-PIC-7-ENTRIES-NEXT: .LBB1_5: # %entry
398+
; RV32I-PIC-7-ENTRIES-NEXT: li a2, 4
399+
; RV32I-PIC-7-ENTRIES-NEXT: beq a0, a2, .LBB1_10
400+
; RV32I-PIC-7-ENTRIES-NEXT: # %bb.6: # %entry
401+
; RV32I-PIC-7-ENTRIES-NEXT: li a2, 5
402+
; RV32I-PIC-7-ENTRIES-NEXT: beq a0, a2, .LBB1_12
403+
; RV32I-PIC-7-ENTRIES-NEXT: # %bb.7: # %entry
404+
; RV32I-PIC-7-ENTRIES-NEXT: li a2, 6
405+
; RV32I-PIC-7-ENTRIES-NEXT: bne a0, a2, .LBB1_14
406+
; RV32I-PIC-7-ENTRIES-NEXT: # %bb.8: # %bb6
407+
; RV32I-PIC-7-ENTRIES-NEXT: li a0, 200
408+
; RV32I-PIC-7-ENTRIES-NEXT: j .LBB1_13
409+
; RV32I-PIC-7-ENTRIES-NEXT: .LBB1_9: # %bb1
410+
; RV32I-PIC-7-ENTRIES-NEXT: li a0, 4
411+
; RV32I-PIC-7-ENTRIES-NEXT: j .LBB1_13
412+
; RV32I-PIC-7-ENTRIES-NEXT: .LBB1_10: # %bb4
413+
; RV32I-PIC-7-ENTRIES-NEXT: li a0, 1
414+
; RV32I-PIC-7-ENTRIES-NEXT: j .LBB1_13
415+
; RV32I-PIC-7-ENTRIES-NEXT: .LBB1_11: # %bb2
416+
; RV32I-PIC-7-ENTRIES-NEXT: li a0, 3
417+
; RV32I-PIC-7-ENTRIES-NEXT: j .LBB1_13
418+
; RV32I-PIC-7-ENTRIES-NEXT: .LBB1_12: # %bb5
419+
; RV32I-PIC-7-ENTRIES-NEXT: li a0, 100
420+
; RV32I-PIC-7-ENTRIES-NEXT: .LBB1_13: # %exit
421+
; RV32I-PIC-7-ENTRIES-NEXT: sw a0, 0(a1)
422+
; RV32I-PIC-7-ENTRIES-NEXT: .LBB1_14: # %exit
423+
; RV32I-PIC-7-ENTRIES-NEXT: ret
424+
;
425+
; RV64I-SMALL-7-ENTRIES-LABEL: above_threshold:
426+
; RV64I-SMALL-7-ENTRIES: # %bb.0: # %entry
427+
; RV64I-SMALL-7-ENTRIES-NEXT: li a2, 3
428+
; RV64I-SMALL-7-ENTRIES-NEXT: blt a2, a0, .LBB1_5
429+
; RV64I-SMALL-7-ENTRIES-NEXT: # %bb.1: # %entry
430+
; RV64I-SMALL-7-ENTRIES-NEXT: li a2, 1
431+
; RV64I-SMALL-7-ENTRIES-NEXT: beq a0, a2, .LBB1_9
432+
; RV64I-SMALL-7-ENTRIES-NEXT: # %bb.2: # %entry
433+
; RV64I-SMALL-7-ENTRIES-NEXT: li a2, 2
434+
; RV64I-SMALL-7-ENTRIES-NEXT: beq a0, a2, .LBB1_11
435+
; RV64I-SMALL-7-ENTRIES-NEXT: # %bb.3: # %entry
436+
; RV64I-SMALL-7-ENTRIES-NEXT: li a2, 3
437+
; RV64I-SMALL-7-ENTRIES-NEXT: bne a0, a2, .LBB1_14
438+
; RV64I-SMALL-7-ENTRIES-NEXT: # %bb.4: # %bb3
439+
; RV64I-SMALL-7-ENTRIES-NEXT: li a0, 2
440+
; RV64I-SMALL-7-ENTRIES-NEXT: j .LBB1_13
441+
; RV64I-SMALL-7-ENTRIES-NEXT: .LBB1_5: # %entry
442+
; RV64I-SMALL-7-ENTRIES-NEXT: li a2, 4
443+
; RV64I-SMALL-7-ENTRIES-NEXT: beq a0, a2, .LBB1_10
444+
; RV64I-SMALL-7-ENTRIES-NEXT: # %bb.6: # %entry
445+
; RV64I-SMALL-7-ENTRIES-NEXT: li a2, 5
446+
; RV64I-SMALL-7-ENTRIES-NEXT: beq a0, a2, .LBB1_12
447+
; RV64I-SMALL-7-ENTRIES-NEXT: # %bb.7: # %entry
448+
; RV64I-SMALL-7-ENTRIES-NEXT: li a2, 6
449+
; RV64I-SMALL-7-ENTRIES-NEXT: bne a0, a2, .LBB1_14
450+
; RV64I-SMALL-7-ENTRIES-NEXT: # %bb.8: # %bb6
451+
; RV64I-SMALL-7-ENTRIES-NEXT: li a0, 200
452+
; RV64I-SMALL-7-ENTRIES-NEXT: j .LBB1_13
453+
; RV64I-SMALL-7-ENTRIES-NEXT: .LBB1_9: # %bb1
454+
; RV64I-SMALL-7-ENTRIES-NEXT: li a0, 4
455+
; RV64I-SMALL-7-ENTRIES-NEXT: j .LBB1_13
456+
; RV64I-SMALL-7-ENTRIES-NEXT: .LBB1_10: # %bb4
457+
; RV64I-SMALL-7-ENTRIES-NEXT: li a0, 1
458+
; RV64I-SMALL-7-ENTRIES-NEXT: j .LBB1_13
459+
; RV64I-SMALL-7-ENTRIES-NEXT: .LBB1_11: # %bb2
460+
; RV64I-SMALL-7-ENTRIES-NEXT: li a0, 3
461+
; RV64I-SMALL-7-ENTRIES-NEXT: j .LBB1_13
462+
; RV64I-SMALL-7-ENTRIES-NEXT: .LBB1_12: # %bb5
463+
; RV64I-SMALL-7-ENTRIES-NEXT: li a0, 100
464+
; RV64I-SMALL-7-ENTRIES-NEXT: .LBB1_13: # %exit
465+
; RV64I-SMALL-7-ENTRIES-NEXT: sw a0, 0(a1)
466+
; RV64I-SMALL-7-ENTRIES-NEXT: .LBB1_14: # %exit
467+
; RV64I-SMALL-7-ENTRIES-NEXT: ret
468+
;
469+
; RV64I-MEDIUM-7-ENTRIES-LABEL: above_threshold:
470+
; RV64I-MEDIUM-7-ENTRIES: # %bb.0: # %entry
471+
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a2, 3
472+
; RV64I-MEDIUM-7-ENTRIES-NEXT: blt a2, a0, .LBB1_5
473+
; RV64I-MEDIUM-7-ENTRIES-NEXT: # %bb.1: # %entry
474+
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a2, 1
475+
; RV64I-MEDIUM-7-ENTRIES-NEXT: beq a0, a2, .LBB1_9
476+
; RV64I-MEDIUM-7-ENTRIES-NEXT: # %bb.2: # %entry
477+
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a2, 2
478+
; RV64I-MEDIUM-7-ENTRIES-NEXT: beq a0, a2, .LBB1_11
479+
; RV64I-MEDIUM-7-ENTRIES-NEXT: # %bb.3: # %entry
480+
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a2, 3
481+
; RV64I-MEDIUM-7-ENTRIES-NEXT: bne a0, a2, .LBB1_14
482+
; RV64I-MEDIUM-7-ENTRIES-NEXT: # %bb.4: # %bb3
483+
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a0, 2
484+
; RV64I-MEDIUM-7-ENTRIES-NEXT: j .LBB1_13
485+
; RV64I-MEDIUM-7-ENTRIES-NEXT: .LBB1_5: # %entry
486+
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a2, 4
487+
; RV64I-MEDIUM-7-ENTRIES-NEXT: beq a0, a2, .LBB1_10
488+
; RV64I-MEDIUM-7-ENTRIES-NEXT: # %bb.6: # %entry
489+
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a2, 5
490+
; RV64I-MEDIUM-7-ENTRIES-NEXT: beq a0, a2, .LBB1_12
491+
; RV64I-MEDIUM-7-ENTRIES-NEXT: # %bb.7: # %entry
492+
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a2, 6
493+
; RV64I-MEDIUM-7-ENTRIES-NEXT: bne a0, a2, .LBB1_14
494+
; RV64I-MEDIUM-7-ENTRIES-NEXT: # %bb.8: # %bb6
495+
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a0, 200
496+
; RV64I-MEDIUM-7-ENTRIES-NEXT: j .LBB1_13
497+
; RV64I-MEDIUM-7-ENTRIES-NEXT: .LBB1_9: # %bb1
498+
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a0, 4
499+
; RV64I-MEDIUM-7-ENTRIES-NEXT: j .LBB1_13
500+
; RV64I-MEDIUM-7-ENTRIES-NEXT: .LBB1_10: # %bb4
501+
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a0, 1
502+
; RV64I-MEDIUM-7-ENTRIES-NEXT: j .LBB1_13
503+
; RV64I-MEDIUM-7-ENTRIES-NEXT: .LBB1_11: # %bb2
504+
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a0, 3
505+
; RV64I-MEDIUM-7-ENTRIES-NEXT: j .LBB1_13
506+
; RV64I-MEDIUM-7-ENTRIES-NEXT: .LBB1_12: # %bb5
507+
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a0, 100
508+
; RV64I-MEDIUM-7-ENTRIES-NEXT: .LBB1_13: # %exit
509+
; RV64I-MEDIUM-7-ENTRIES-NEXT: sw a0, 0(a1)
510+
; RV64I-MEDIUM-7-ENTRIES-NEXT: .LBB1_14: # %exit
511+
; RV64I-MEDIUM-7-ENTRIES-NEXT: ret
512+
;
513+
; RV64I-PIC-7-ENTRIES-LABEL: above_threshold:
514+
; RV64I-PIC-7-ENTRIES: # %bb.0: # %entry
515+
; RV64I-PIC-7-ENTRIES-NEXT: li a2, 3
516+
; RV64I-PIC-7-ENTRIES-NEXT: blt a2, a0, .LBB1_5
517+
; RV64I-PIC-7-ENTRIES-NEXT: # %bb.1: # %entry
518+
; RV64I-PIC-7-ENTRIES-NEXT: li a2, 1
519+
; RV64I-PIC-7-ENTRIES-NEXT: beq a0, a2, .LBB1_9
520+
; RV64I-PIC-7-ENTRIES-NEXT: # %bb.2: # %entry
521+
; RV64I-PIC-7-ENTRIES-NEXT: li a2, 2
522+
; RV64I-PIC-7-ENTRIES-NEXT: beq a0, a2, .LBB1_11
523+
; RV64I-PIC-7-ENTRIES-NEXT: # %bb.3: # %entry
524+
; RV64I-PIC-7-ENTRIES-NEXT: li a2, 3
525+
; RV64I-PIC-7-ENTRIES-NEXT: bne a0, a2, .LBB1_14
526+
; RV64I-PIC-7-ENTRIES-NEXT: # %bb.4: # %bb3
527+
; RV64I-PIC-7-ENTRIES-NEXT: li a0, 2
528+
; RV64I-PIC-7-ENTRIES-NEXT: j .LBB1_13
529+
; RV64I-PIC-7-ENTRIES-NEXT: .LBB1_5: # %entry
530+
; RV64I-PIC-7-ENTRIES-NEXT: li a2, 4
531+
; RV64I-PIC-7-ENTRIES-NEXT: beq a0, a2, .LBB1_10
532+
; RV64I-PIC-7-ENTRIES-NEXT: # %bb.6: # %entry
533+
; RV64I-PIC-7-ENTRIES-NEXT: li a2, 5
534+
; RV64I-PIC-7-ENTRIES-NEXT: beq a0, a2, .LBB1_12
535+
; RV64I-PIC-7-ENTRIES-NEXT: # %bb.7: # %entry
536+
; RV64I-PIC-7-ENTRIES-NEXT: li a2, 6
537+
; RV64I-PIC-7-ENTRIES-NEXT: bne a0, a2, .LBB1_14
538+
; RV64I-PIC-7-ENTRIES-NEXT: # %bb.8: # %bb6
539+
; RV64I-PIC-7-ENTRIES-NEXT: li a0, 200
540+
; RV64I-PIC-7-ENTRIES-NEXT: j .LBB1_13
541+
; RV64I-PIC-7-ENTRIES-NEXT: .LBB1_9: # %bb1
542+
; RV64I-PIC-7-ENTRIES-NEXT: li a0, 4
543+
; RV64I-PIC-7-ENTRIES-NEXT: j .LBB1_13
544+
; RV64I-PIC-7-ENTRIES-NEXT: .LBB1_10: # %bb4
545+
; RV64I-PIC-7-ENTRIES-NEXT: li a0, 1
546+
; RV64I-PIC-7-ENTRIES-NEXT: j .LBB1_13
547+
; RV64I-PIC-7-ENTRIES-NEXT: .LBB1_11: # %bb2
548+
; RV64I-PIC-7-ENTRIES-NEXT: li a0, 3
549+
; RV64I-PIC-7-ENTRIES-NEXT: j .LBB1_13
550+
; RV64I-PIC-7-ENTRIES-NEXT: .LBB1_12: # %bb5
551+
; RV64I-PIC-7-ENTRIES-NEXT: li a0, 100
552+
; RV64I-PIC-7-ENTRIES-NEXT: .LBB1_13: # %exit
553+
; RV64I-PIC-7-ENTRIES-NEXT: sw a0, 0(a1)
554+
; RV64I-PIC-7-ENTRIES-NEXT: .LBB1_14: # %exit
555+
; RV64I-PIC-7-ENTRIES-NEXT: ret
280556
entry:
281557
switch i32 %in, label %exit [
282558
i32 1, label %bb1

0 commit comments

Comments
 (0)