[BOLT] Clear operands when creating new instructions. NFCI (#85191)

Reset operand list whenever we create a new instruction via a parameter
passed by reference. Most functions were already doing this, but there
are several places missing the reset. Potentially, if we don not clear
the list it could lead to invalid instruction operands. But the existing
code is unaffected.

Author: maksfb

bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp

@@ -1387,6 +1387,7 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
   void createIndirectBranch(MCInst &Inst, MCPhysReg MemBaseReg,
                             int64_t Disp) const {
     Inst.setOpcode(AArch64::BR);
+    Inst.clear();
     Inst.addOperand(MCOperand::createReg(MemBaseReg));
   }
 

bolt/lib/Target/X86/X86MCPlusBuilder.cpp

@@ -2367,11 +2367,13 @@ class X86MCPlusBuilder : public MCPlusBuilder {
 
   bool createNoop(MCInst &Inst) const override {
     Inst.setOpcode(X86::NOOP);
+    Inst.clear();
     return true;
   }
 
   bool createReturn(MCInst &Inst) const override {
     Inst.setOpcode(X86::RET64);
+    Inst.clear();
     return true;
   }
 
@@ -2732,6 +2734,7 @@ class X86MCPlusBuilder : public MCPlusBuilder {
   bool createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
                           MCContext *Ctx) const override {
     Inst.setOpcode(X86::JMP_1);
+    Inst.clear();
     Inst.addOperand(MCOperand::createExpr(
         MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx)));
     return true;
@@ -2740,6 +2743,7 @@ class X86MCPlusBuilder : public MCPlusBuilder {
   bool createCall(MCInst &Inst, const MCSymbol *Target,
                   MCContext *Ctx) override {
     Inst.setOpcode(X86::CALL64pcrel32);
+    Inst.clear();
     Inst.addOperand(MCOperand::createExpr(
         MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx)));
     return true;
@@ -3066,6 +3070,7 @@ class X86MCPlusBuilder : public MCPlusBuilder {
   void createSwap(MCInst &Inst, MCPhysReg Source, MCPhysReg MemBaseReg,
                   int64_t Disp) const {
     Inst.setOpcode(X86::XCHG64rm);
+    Inst.clear();
     Inst.addOperand(MCOperand::createReg(Source));
     Inst.addOperand(MCOperand::createReg(Source));
     Inst.addOperand(MCOperand::createReg(MemBaseReg));      // BaseReg
@@ -3078,6 +3083,7 @@ class X86MCPlusBuilder : public MCPlusBuilder {
   void createIndirectBranch(MCInst &Inst, MCPhysReg MemBaseReg,
                             int64_t Disp) const {
     Inst.setOpcode(X86::JMP64m);
+    Inst.clear();
     Inst.addOperand(MCOperand::createReg(MemBaseReg));      // BaseReg
     Inst.addOperand(MCOperand::createImm(1));               // ScaleAmt
     Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg
@@ -3543,6 +3549,7 @@ class X86MCPlusBuilder : public MCPlusBuilder {
   bool createMove(MCInst &Inst, const MCSymbol *Src, unsigned Reg,
                   MCContext *Ctx) const {
     Inst.setOpcode(X86::MOV64rm);
+    Inst.clear();
     Inst.addOperand(MCOperand::createReg(Reg));
     Inst.addOperand(MCOperand::createReg(X86::RIP));        // BaseReg
     Inst.addOperand(MCOperand::createImm(1));               // ScaleAmt
@@ -3558,6 +3565,7 @@ class X86MCPlusBuilder : public MCPlusBuilder {
   bool createLea(MCInst &Inst, const MCSymbol *Src, unsigned Reg,
                  MCContext *Ctx) const {
     Inst.setOpcode(X86::LEA64r);
+    Inst.clear();
     Inst.addOperand(MCOperand::createReg(Reg));
     Inst.addOperand(MCOperand::createReg(X86::RIP));        // BaseReg
     Inst.addOperand(MCOperand::createImm(1));               // ScaleAmt