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[flang] Add the endianness check for vec_sld and vec_sldw intrinsics
Differential Revision: https://reviews.llvm.org/D158189
1 parent d34e97c commit 59c59a3

11 files changed

+2852
-2133
lines changed

‎flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp

Lines changed: 21 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -924,15 +924,18 @@ checkPPCMathOperationsRange(llvm::StringRef name) {
924924

925925
// Helper functions for vector element ordering.
926926
bool PPCIntrinsicLibrary::isBEVecElemOrderOnLE() {
927-
return (Fortran::evaluate::isHostLittleEndian &&
927+
const auto triple{fir::getTargetTriple(builder.getModule())};
928+
return (triple.isLittleEndian() &&
928929
converter->getLoweringOptions().getNoPPCNativeVecElemOrder());
929930
}
930931
bool PPCIntrinsicLibrary::isNativeVecElemOrderOnLE() {
931-
return (Fortran::evaluate::isHostLittleEndian &&
932+
const auto triple{fir::getTargetTriple(builder.getModule())};
933+
return (triple.isLittleEndian() &&
932934
!converter->getLoweringOptions().getNoPPCNativeVecElemOrder());
933935
}
934936
bool PPCIntrinsicLibrary::changeVecElemOrder() {
935-
return (Fortran::evaluate::isHostLittleEndian !=
937+
const auto triple{fir::getTargetTriple(builder.getModule())};
938+
return (triple.isLittleEndian() !=
936939
converter->getLoweringOptions().getNoPPCNativeVecElemOrder());
937940
}
938941

@@ -2205,12 +2208,19 @@ PPCIntrinsicLibrary::genVecShift(mlir::Type resultType,
22052208
shiftVal = shiftVal << 2;
22062209
shiftVal &= 0xF;
22072210
llvm::SmallVector<int64_t, 16> mask;
2208-
for (int i = 16; i < 32; ++i)
2209-
mask.push_back(i - shiftVal);
2210-
2211-
// Shuffle with mask
2212-
shftRes = builder.create<mlir::vector::ShuffleOp>(loc, mlirVecArgs[1],
2213-
mlirVecArgs[0], mask);
2211+
// Shuffle with mask based on the endianness
2212+
const auto triple{fir::getTargetTriple(builder.getModule())};
2213+
if (triple.isLittleEndian()) {
2214+
for (int i = 16; i < 32; ++i)
2215+
mask.push_back(i - shiftVal);
2216+
shftRes = builder.create<mlir::vector::ShuffleOp>(loc, mlirVecArgs[1],
2217+
mlirVecArgs[0], mask);
2218+
} else {
2219+
for (int i = 0; i < 16; ++i)
2220+
mask.push_back(i + shiftVal);
2221+
shftRes = builder.create<mlir::vector::ShuffleOp>(loc, mlirVecArgs[0],
2222+
mlirVecArgs[1], mask);
2223+
}
22142224

22152225
// Bitcast to the original type
22162226
if (shftRes.getType() != mlirTyArgs[0])
@@ -2593,7 +2603,8 @@ void PPCIntrinsicLibrary::genMmaIntr(llvm::ArrayRef<fir::ExtendedValue> args) {
25932603
} else if (HandlerOp == MMAHandlerOp::SubToFuncReverseArgOnLE) {
25942604
// Reverse argument order on little-endian target only.
25952605
// The reversal does not depend on the setting of non-native-order option.
2596-
if (Fortran::evaluate::isHostLittleEndian) {
2606+
const auto triple{fir::getTargetTriple(builder.getModule())};
2607+
if (triple.isLittleEndian()) {
25972608
// Load the arguments in reverse order.
25982609
argStart = args.size() - 1;
25992610
// The first argument becomes function result. Stop at the second

‎flang/test/Lower/PowerPC/ppc-vec-extract-elem-order.f90

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
! RUN: bbc -emit-fir -fno-ppc-native-vector-element-order %s -o - | FileCheck --check-prefixes="FIR" %s
2-
! RUN: %flang_fc1 -emit-llvm -fno-ppc-native-vector-element-order %s -o - | FileCheck --check-prefixes="LLVMIR" %s
1+
! RUN: %flang_fc1 -emit-fir %s -fno-ppc-native-vector-element-order -triple ppc64le-unknown-linux -o - | FileCheck --check-prefixes="FIR" %s
2+
! RUN: %flang_fc1 -emit-llvm %s -fno-ppc-native-vector-element-order -triple ppc64le-unknown-linux -o - | FileCheck --check-prefixes="LLVMIR" %s
33
! REQUIRES: target=powerpc{{.*}}
44

55
!CHECK-LABEL: vec_extract_testr4i8

‎flang/test/Lower/PowerPC/ppc-vec-insert-elem-order.f90

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
! RUN: bbc -emit-fir -fno-ppc-native-vector-element-order %s -o - | FileCheck --check-prefixes="FIR" %s
2-
! RUN: %flang_fc1 -emit-llvm -fno-ppc-native-vector-element-order %s -o - | FileCheck --check-prefixes="LLVMIR" %s
1+
! RUN: %flang_fc1 -emit-fir %s -fno-ppc-native-vector-element-order -triple ppc64le-unknown-linux -o - | FileCheck --check-prefixes="FIR" %s
2+
! RUN: %flang_fc1 -emit-llvm %s -fno-ppc-native-vector-element-order -triple ppc64le-unknown-linux -o - | FileCheck --check-prefixes="LLVMIR" %s
33
! REQUIRES: target=powerpc{{.*}}
44

55
!CHECK-LABEL: vec_insert_testf32i64

‎flang/test/Lower/PowerPC/ppc-vec-load-elem-order.f90

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
! RUN: bbc -emit-fir %s -fno-ppc-native-vector-element-order -o - | FileCheck --check-prefixes="FIR" %s
2-
! RUN: %flang_fc1 -emit-llvm %s -fno-ppc-native-vector-element-order -o - | FileCheck --check-prefixes="LLVMIR" %s
1+
! RUN: %flang_fc1 -emit-fir %s -fno-ppc-native-vector-element-order -triple ppc64le-unknown-linux -o - | FileCheck --check-prefixes="FIR" %s
2+
! RUN: %flang_fc1 -emit-llvm %s -fno-ppc-native-vector-element-order -triple ppc64le-unknown-linux -o - | FileCheck --check-prefixes="LLVMIR" %s
33
! REQUIRES: target=powerpc{{.*}}
44

55
!-------------------

‎flang/test/Lower/PowerPC/ppc-vec-merge-elem-order.f90

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
! RUN: bbc -emit-fir %s -fno-ppc-native-vector-element-order -o - | FileCheck --check-prefixes="FIR" %s
2-
! RUN: %flang_fc1 -emit-llvm %s -fno-ppc-native-vector-element-order -o - | FileCheck --check-prefixes="LLVMIR" %s
1+
! RUN: %flang_fc1 -emit-fir %s -fno-ppc-native-vector-element-order -triple ppc64le-unknown-linux -o - | FileCheck --check-prefixes="FIR" %s
2+
! RUN: %flang_fc1 -emit-llvm %s -fno-ppc-native-vector-element-order -triple ppc64le-unknown-linux -o - | FileCheck --check-prefixes="LLVMIR" %s
33
! REQUIRES: target=powerpc{{.*}}
44

55
!-----------------

‎flang/test/Lower/PowerPC/ppc-vec-perm-elem-order.f90

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
! RUN: bbc -emit-fir %s -fno-ppc-native-vector-element-order -o - | FileCheck --check-prefixes="FIR" %s
2-
! RUN: %flang_fc1 -emit-llvm %s -fno-ppc-native-vector-element-order -o - | FileCheck --check-prefixes="LLVMIR" %s
1+
! RUN: %flang_fc1 -emit-fir %s -fno-ppc-native-vector-element-order -triple ppc64le-unknown-linux -o - | FileCheck --check-prefixes="FIR" %s
2+
! RUN: %flang_fc1 -emit-llvm %s -fno-ppc-native-vector-element-order -triple ppc64le-unknwon-linux -o - | FileCheck --check-prefixes="LLVMIR" %s
33
! REQUIRES: target=powerpc{{.*}}
44

55
!----------------

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