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kosarevkosarev
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[AMDGPU][True16] Support source DPP operands. (#79025)
1 parent 47bcc91 commit 5a45876

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10 files changed

+277
-190
lines changed

10 files changed

+277
-190
lines changed

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -346,7 +346,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
346346
}
347347

348348
bool isVRegWithInputMods() const;
349-
bool isT16VRegWithInputMods() const;
349+
template <bool IsFake16> bool isT16VRegWithInputMods() const;
350350

351351
bool isSDWAOperand(MVT type) const;
352352
bool isSDWAFP16Operand() const;
@@ -2054,8 +2054,9 @@ bool AMDGPUOperand::isVRegWithInputMods() const {
20542054
AsmParser->getFeatureBits()[AMDGPU::FeatureDPALU_DPP]);
20552055
}
20562056

2057-
bool AMDGPUOperand::isT16VRegWithInputMods() const {
2058-
return isRegClass(AMDGPU::VGPR_32_Lo128RegClassID);
2057+
template <bool IsFake16> bool AMDGPUOperand::isT16VRegWithInputMods() const {
2058+
return isRegClass(IsFake16 ? AMDGPU::VGPR_32_Lo128RegClassID
2059+
: AMDGPU::VGPR_16_Lo128RegClassID);
20592060
}
20602061

20612062
bool AMDGPUOperand::isSDWAOperand(MVT type) const {

‎llvm/lib/Target/AMDGPU/BUFInstructions.td

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -485,8 +485,8 @@ class MUBUF_Load_Pseudo <string opName,
485485
list<dag> pattern=[],
486486
// Workaround bug bz30254
487487
int addrKindCopy = addrKind,
488-
RegisterClass vdata_rc = getVregSrcForVT<vdata_vt>.ret,
489-
RegisterOperand vdata_op = getLdStVDataRegisterOperand<vdata_rc, isTFE>.ret>
488+
RegisterOperand vdata_rc = getVregSrcForVT<vdata_vt>.ret,
489+
RegisterOperand vdata_op = getLdStVDataRegisterOperand<vdata_rc.RegClass, isTFE>.ret>
490490
: MUBUF_Pseudo<opName,
491491
!if(!or(isLds, isLdsOpc), (outs), (outs vdata_op:$vdata)),
492492
!con(getMUBUFIns<addrKindCopy, [], isTFE, hasGFX12Enc>.ret,
@@ -601,7 +601,7 @@ class MUBUF_Store_Pseudo <string opName,
601601
int addrKindCopy = addrKind>
602602
: MUBUF_Pseudo<opName,
603603
(outs),
604-
getMUBUFIns<addrKindCopy, [getVregSrcForVT<store_vt>.ret], isTFE, hasGFX12Enc>.ret,
604+
getMUBUFIns<addrKindCopy, [getVregSrcForVT<store_vt>.ret.RegClass], isTFE, hasGFX12Enc>.ret,
605605
getMUBUFAsmOps<addrKindCopy, 0, 0, isTFE>.ret,
606606
pattern>,
607607
MUBUF_SetupAddr<addrKindCopy> {
@@ -1569,27 +1569,28 @@ multiclass BufferAtomicCmpSwapPat_Common<ValueType vt, ValueType data_vt, string
15691569
# !if(!eq(RtnMode, "ret"), "", "_noret")
15701570
# "_" # vt.Size);
15711571
defvar InstSuffix = !if(!eq(RtnMode, "ret"), "_RTN", "");
1572+
defvar data_vt_RC = getVregSrcForVT<data_vt>.ret.RegClass;
15721573

15731574
let AddedComplexity = !if(!eq(RtnMode, "ret"), 0, 1) in {
15741575
defvar OffsetResDag = (!cast<MUBUF_Pseudo>(Inst # "_OFFSET" # InstSuffix)
1575-
getVregSrcForVT<data_vt>.ret:$vdata_in, SReg_128:$srsrc, SCSrc_b32:$soffset,
1576+
data_vt_RC:$vdata_in, SReg_128:$srsrc, SCSrc_b32:$soffset,
15761577
offset:$offset);
15771578
def : GCNPat<
15781579
(vt (Op (MUBUFOffset v4i32:$srsrc, i32:$soffset, i32:$offset), data_vt:$vdata_in)),
15791580
!if(!eq(RtnMode, "ret"),
1580-
(EXTRACT_SUBREG (vt (COPY_TO_REGCLASS OffsetResDag, getVregSrcForVT<data_vt>.ret)),
1581+
(EXTRACT_SUBREG (vt (COPY_TO_REGCLASS OffsetResDag, data_vt_RC)),
15811582
!if(!eq(vt, i32), sub0, sub0_sub1)),
15821583
OffsetResDag)
15831584
>;
15841585

15851586
defvar Addr64ResDag = (!cast<MUBUF_Pseudo>(Inst # "_ADDR64" # InstSuffix)
1586-
getVregSrcForVT<data_vt>.ret:$vdata_in, VReg_64:$vaddr, SReg_128:$srsrc,
1587+
data_vt_RC:$vdata_in, VReg_64:$vaddr, SReg_128:$srsrc,
15871588
SCSrc_b32:$soffset, offset:$offset);
15881589
def : GCNPat<
15891590
(vt (Op (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i32:$offset),
15901591
data_vt:$vdata_in)),
15911592
!if(!eq(RtnMode, "ret"),
1592-
(EXTRACT_SUBREG (vt (COPY_TO_REGCLASS Addr64ResDag, getVregSrcForVT<data_vt>.ret)),
1593+
(EXTRACT_SUBREG (vt (COPY_TO_REGCLASS Addr64ResDag, data_vt_RC)),
15931594
!if(!eq(vt, i32), sub0, sub0_sub1)),
15941595
Addr64ResDag)
15951596
>;
@@ -1820,7 +1821,7 @@ multiclass SIBufferAtomicCmpSwapPat_Common<ValueType vt, ValueType data_vt, stri
18201821
(extract_cpol_set_glc $auxiliary),
18211822
(extract_cpol $auxiliary));
18221823
defvar SrcRC = getVregSrcForVT<vt>.ret;
1823-
defvar DataRC = getVregSrcForVT<data_vt>.ret;
1824+
defvar DataRC = getVregSrcForVT<data_vt>.ret.RegClass;
18241825
defvar SubLo = !if(!eq(vt, i32), sub0, sub0_sub1);
18251826
defvar SubHi = !if(!eq(vt, i32), sub1, sub2_sub3);
18261827

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp

Lines changed: 42 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -562,7 +562,48 @@ void AMDGPUMCCodeEmitter::getMachineOpValue(const MCInst &MI,
562562
void AMDGPUMCCodeEmitter::getMachineOpValueT16(
563563
const MCInst &MI, unsigned OpNo, APInt &Op,
564564
SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
565-
llvm_unreachable("TODO: Implement getMachineOpValueT16().");
565+
const MCOperand &MO = MI.getOperand(OpNo);
566+
if (MO.isReg()) {
567+
unsigned Enc = MRI.getEncodingValue(MO.getReg());
568+
unsigned Idx = Enc & AMDGPU::HWEncoding::REG_IDX_MASK;
569+
bool IsVGPR = Enc & AMDGPU::HWEncoding::IS_VGPR_OR_AGPR;
570+
Op = Idx | (IsVGPR << 8);
571+
return;
572+
}
573+
getMachineOpValueCommon(MI, MO, OpNo, Op, Fixups, STI);
574+
// VGPRs include the suffix/op_sel bit in the register encoding, but
575+
// immediates and SGPRs include it in src_modifiers. Therefore, copy the
576+
// op_sel bit from the src operands into src_modifier operands if Op is
577+
// src_modifiers and the corresponding src is a VGPR
578+
int SrcMOIdx = -1;
579+
assert(OpNo < INT_MAX);
580+
if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI.getOpcode(),
581+
AMDGPU::OpName::src0_modifiers)) {
582+
SrcMOIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0);
583+
int VDstMOIdx =
584+
AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst);
585+
if (VDstMOIdx != -1) {
586+
auto DstReg = MI.getOperand(VDstMOIdx).getReg();
587+
if (AMDGPU::isHi(DstReg, MRI))
588+
Op |= SISrcMods::DST_OP_SEL;
589+
}
590+
} else if ((int)OpNo == AMDGPU::getNamedOperandIdx(
591+
MI.getOpcode(), AMDGPU::OpName::src1_modifiers))
592+
SrcMOIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src1);
593+
else if ((int)OpNo == AMDGPU::getNamedOperandIdx(
594+
MI.getOpcode(), AMDGPU::OpName::src2_modifiers))
595+
SrcMOIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src2);
596+
if (SrcMOIdx == -1)
597+
return;
598+
599+
const MCOperand &SrcMO = MI.getOperand(SrcMOIdx);
600+
if (!SrcMO.isReg())
601+
return;
602+
auto SrcReg = SrcMO.getReg();
603+
if (AMDGPU::isSGPR(SrcReg, &MRI))
604+
return;
605+
if (AMDGPU::isHi(SrcReg, MRI))
606+
Op |= SISrcMods::OP_SEL_0;
566607
}
567608

568609
void AMDGPUMCCodeEmitter::getMachineOpValueT16Lo128(

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 55 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -1223,17 +1223,20 @@ def FPVRegInputModsMatchClass : AsmOperandClass {
12231223
let PredicateMethod = "isVRegWithInputMods";
12241224
}
12251225

1226-
def FPT16VRegInputModsMatchClass : AsmOperandClass {
1227-
let Name = "T16VRegWithFPInputMods";
1226+
class FPT16VRegInputModsMatchClass<bit IsFake16> : AsmOperandClass {
1227+
let Name = !if(IsFake16, "Fake16VRegWithFPInputMods",
1228+
"T16VRegWithFPInputMods");
12281229
let ParserMethod = "parseRegWithFPInputMods";
1229-
let PredicateMethod = "isT16VRegWithInputMods";
1230+
let PredicateMethod = "isT16VRegWithInputMods<" #
1231+
!if(IsFake16, "true", "false") # ">";
12301232
}
12311233

12321234
def FPVRegInputMods : InputMods <FPVRegInputModsMatchClass> {
12331235
let PrintMethod = "printOperandAndFPInputMods";
12341236
}
12351237

1236-
def FPT16VRegInputMods : InputMods <FPT16VRegInputModsMatchClass> {
1238+
class FPT16VRegInputMods<bit IsFake16>
1239+
: InputMods <FPT16VRegInputModsMatchClass<IsFake16>> {
12371240
let PrintMethod = "printOperandAndFPInputMods";
12381241
}
12391242

@@ -1265,13 +1268,16 @@ def IntVRegInputModsMatchClass : AsmOperandClass {
12651268
let PredicateMethod = "isVRegWithInputMods";
12661269
}
12671270

1268-
def IntT16VRegInputModsMatchClass : AsmOperandClass {
1269-
let Name = "T16VRegWithIntInputMods";
1271+
class IntT16VRegInputModsMatchClass<bit IsFake16> : AsmOperandClass {
1272+
let Name = !if(IsFake16, "Fake16VRegWithIntInputMods",
1273+
"T16VRegWithIntInputMods");
12701274
let ParserMethod = "parseRegWithIntInputMods";
1271-
let PredicateMethod = "isT16VRegWithInputMods";
1275+
let PredicateMethod = "isT16VRegWithInputMods<" #
1276+
!if(IsFake16, "true", "false") # ">";
12721277
}
12731278

1274-
def IntT16VRegInputMods : InputMods <IntT16VRegInputModsMatchClass> {
1279+
class IntT16VRegInputMods<bit IsFake16>
1280+
: InputMods <IntT16VRegInputModsMatchClass<IsFake16>> {
12751281
let PrintMethod = "printOperandAndIntInputMods";
12761282
}
12771283

@@ -1510,25 +1516,17 @@ class getSOPSrcForVT<ValueType VT> {
15101516
}
15111517

15121518
// Returns the vreg register class to use for source operand given VT
1513-
class getVregSrcForVT<ValueType VT> {
1514-
RegisterClass ret = !if(!eq(VT.Size, 128), VReg_128,
1515-
!if(!eq(VT.Size, 96), VReg_96,
1516-
!if(!eq(VT.Size, 64), VReg_64,
1517-
!if(!eq(VT.Size, 48), VReg_64,
1518-
VGPR_32))));
1519-
}
1520-
1521-
class getVregSrcForVT_t16<ValueType VT, bit IsFake16 = 1> {
1522-
RegisterClass ret = !if(!eq(VT.Size, 128), VReg_128,
1523-
!if(!eq(VT.Size, 96), VReg_96,
1524-
!if(!eq(VT.Size, 64), VReg_64,
1525-
!if(!eq(VT.Size, 48), VReg_64,
1526-
!if(!eq(VT.Size, 16),
1527-
!if(IsFake16, VGPR_32_Lo128, VGPR_16_Lo128),
1528-
VGPR_32)))));
1529-
1530-
RegisterOperand op = !if (!and(!eq(VT.Size, 16), !not(IsFake16)),
1531-
VGPRSrc_16_Lo128, RegisterOperand<ret>);
1519+
class getVregSrcForVT<ValueType VT, bit IsTrue16 = 0, bit IsFake16 = 0> {
1520+
RegisterOperand ret =
1521+
!if (!eq(VT.Size, 128), RegisterOperand<VReg_128>,
1522+
!if (!eq(VT.Size, 96), RegisterOperand<VReg_96>,
1523+
!if (!eq(VT.Size, 64), RegisterOperand<VReg_64>,
1524+
!if (!eq(VT.Size, 48), RegisterOperand<VReg_64>,
1525+
!if (!eq(VT.Size, 16),
1526+
!if (IsTrue16,
1527+
!if (IsFake16, VGPRSrc_32_Lo128, VGPRSrc_16_Lo128),
1528+
RegisterOperand<VGPR_32>),
1529+
RegisterOperand<VGPR_32>)))));
15321530
}
15331531

15341532
class getSDWASrcForVT <ValueType VT> {
@@ -1635,13 +1633,13 @@ class getSrcModDPP <ValueType VT> {
16351633
Operand ret = !if(VT.isFP, FPVRegInputMods, IntVRegInputMods);
16361634
}
16371635

1638-
class getSrcModDPP_t16 <ValueType VT> {
1636+
class getSrcModDPP_t16 <ValueType VT, bit IsFake16 = 1> {
16391637
Operand ret =
16401638
!if (VT.isFP,
16411639
!if (!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)),
1642-
FPT16VRegInputMods, FPVRegInputMods),
1643-
!if (!eq(VT.Value, i16.Value), IntT16VRegInputMods,
1644-
IntVRegInputMods));
1640+
FPT16VRegInputMods<IsFake16>, FPVRegInputMods),
1641+
!if (!eq(VT.Value, i16.Value),
1642+
IntT16VRegInputMods<IsFake16>, IntVRegInputMods));
16451643
}
16461644

16471645
// Return type of input modifiers operand for specified input operand for DPP
@@ -1784,10 +1782,9 @@ class getInsVOP3OpSel <RegisterOperand Src0RC, RegisterOperand Src1RC,
17841782
Src0Mod, Src1Mod, Src2Mod, /*HasOpSel=*/1>.ret;
17851783
}
17861784

1787-
class getInsDPPBase <RegisterOperand OldRC, RegisterClass Src0RC, RegisterClass Src1RC,
1788-
RegisterClass Src2RC, int NumSrcArgs, bit HasModifiers,
1789-
Operand Src0Mod, Operand Src1Mod, Operand Src2Mod, bit HasOld> {
1790-
1785+
class getInsDPPBase <RegisterOperand OldRC, RegisterOperand Src0RC, RegisterOperand Src1RC,
1786+
RegisterOperand Src2RC, int NumSrcArgs, bit HasModifiers,
1787+
Operand Src0Mod, Operand Src1Mod, Operand Src2Mod, bit HasOld> {
17911788
dag ret = !if(!eq(NumSrcArgs, 0),
17921789
// VOP1 without input operands (V_NOP)
17931790
(ins ),
@@ -1827,26 +1824,26 @@ class getInsDPPBase <RegisterOperand OldRC, RegisterClass Src0RC, RegisterClass
18271824
);
18281825
}
18291826

1830-
class getInsDPP <RegisterOperand OldRC, RegisterClass Src0RC, RegisterClass Src1RC,
1831-
RegisterClass Src2RC, int NumSrcArgs, bit HasModifiers,
1827+
class getInsDPP <RegisterOperand OldRC, RegisterOperand Src0RC, RegisterOperand Src1RC,
1828+
RegisterOperand Src2RC, int NumSrcArgs, bit HasModifiers,
18321829
Operand Src0Mod, Operand Src1Mod, Operand Src2Mod, bit HasOld = 1> {
18331830
dag ret = !con(getInsDPPBase<OldRC, Src0RC, Src1RC, Src2RC, NumSrcArgs,
18341831
HasModifiers, Src0Mod, Src1Mod, Src2Mod, HasOld>.ret,
18351832
(ins dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
18361833
bank_mask:$bank_mask, bound_ctrl:$bound_ctrl));
18371834
}
18381835

1839-
class getInsDPP16 <RegisterOperand OldRC, RegisterClass Src0RC, RegisterClass Src1RC,
1840-
RegisterClass Src2RC, int NumSrcArgs, bit HasModifiers,
1841-
Operand Src0Mod, Operand Src1Mod, Operand Src2Mod, bit HasOld = 1> {
1836+
class getInsDPP16 <RegisterOperand OldRC, RegisterOperand Src0RC, RegisterOperand Src1RC,
1837+
RegisterOperand Src2RC, int NumSrcArgs, bit HasModifiers,
1838+
Operand Src0Mod, Operand Src1Mod, Operand Src2Mod, bit HasOld = 1> {
18421839
dag ret = !con(getInsDPP<OldRC, Src0RC, Src1RC, Src2RC, NumSrcArgs,
18431840
HasModifiers, Src0Mod, Src1Mod, Src2Mod, HasOld>.ret,
18441841
(ins FI:$fi));
18451842
}
18461843

1847-
class getInsDPP8 <RegisterOperand OldRC, RegisterClass Src0RC, RegisterClass Src1RC,
1848-
RegisterClass Src2RC, int NumSrcArgs, bit HasModifiers,
1849-
Operand Src0Mod, Operand Src1Mod, Operand Src2Mod, bit HasOld = 1> {
1844+
class getInsDPP8 <RegisterOperand OldRC, RegisterOperand Src0RC, RegisterOperand Src1RC,
1845+
RegisterOperand Src2RC, int NumSrcArgs, bit HasModifiers,
1846+
Operand Src0Mod, Operand Src1Mod, Operand Src2Mod, bit HasOld = 1> {
18501847
dag ret = !con(getInsDPPBase<OldRC, Src0RC, Src1RC, Src2RC, NumSrcArgs,
18511848
HasModifiers, Src0Mod, Src1Mod, Src2Mod, HasOld>.ret,
18521849
(ins dpp8:$dpp8, FI:$fi));
@@ -2251,13 +2248,13 @@ class VOPProfile <list<ValueType> _ArgVT, bit _EnableClamp = 0> {
22512248
field RegisterOperand DstRCVOP3DPP = DstRC64;
22522249
field RegisterOperand DstRCSDWA = getSDWADstForVT<DstVT>.ret;
22532250
field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT, IsTrue16>.ret;
2254-
field RegisterOperand Src1RC32 = RegisterOperand<getVregSrcForVT<Src1VT>.ret>;
2251+
field RegisterOperand Src1RC32 = getVregSrcForVT<Src1VT>.ret;
22552252
field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
22562253
field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
22572254
field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
2258-
field RegisterClass Src0DPP = getVregSrcForVT<Src0VT>.ret;
2259-
field RegisterClass Src1DPP = getVregSrcForVT<Src1VT>.ret;
2260-
field RegisterClass Src2DPP = getVregSrcForVT<Src2VT>.ret;
2255+
field RegisterOperand Src0DPP = getVregSrcForVT<Src0VT>.ret;
2256+
field RegisterOperand Src1DPP = getVregSrcForVT<Src1VT>.ret;
2257+
field RegisterOperand Src2DPP = getVregSrcForVT<Src2VT>.ret;
22612258
field RegisterOperand Src0VOP3DPP = VGPRSrc_32;
22622259
field RegisterOperand Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT>.ret;
22632260
field RegisterOperand Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT>.ret;
@@ -2443,13 +2440,13 @@ class VOPProfile_True16<VOPProfile P> : VOPProfile<P.ArgVT> {
24432440
let DstRC = getVALUDstForVT<DstVT, 1 /*IsTrue16*/, 0 /*IsVOP3Encoding*/>.ret;
24442441
let DstRC64 = getVALUDstForVT<DstVT>.ret;
24452442
let Src0RC32 = getVOPSrc0ForVT<Src0VT, 1 /*IsTrue16*/, 0 /*IsFake16*/>.ret;
2446-
let Src1RC32 = getVregSrcForVT_t16<Src1VT, 0 /*IsFake16*/>.op;
2447-
let Src0DPP = getVregSrcForVT_t16<Src0VT>.ret;
2448-
let Src1DPP = getVregSrcForVT_t16<Src1VT>.ret;
2449-
let Src2DPP = getVregSrcForVT_t16<Src2VT>.ret;
2450-
let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret;
2451-
let Src1ModDPP = getSrcModDPP_t16<Src1VT>.ret;
2452-
let Src2ModDPP = getSrcModDPP_t16<Src2VT>.ret;
2443+
let Src1RC32 = getVregSrcForVT<Src1VT, 1 /*IsTrue16*/, 0 /*IsFake16*/>.ret;
2444+
let Src0DPP = getVregSrcForVT<Src0VT, 1 /*IsTrue16*/, 0 /*IsFake16*/>.ret;
2445+
let Src1DPP = getVregSrcForVT<Src1VT, 1 /*IsTrue16*/, 0 /*IsFake16*/>.ret;
2446+
let Src2DPP = getVregSrcForVT<Src2VT, 1 /*IsTrue16*/, 0 /*IsFake16*/>.ret;
2447+
let Src0ModDPP = getSrcModDPP_t16<Src0VT, 0 /*IsFake16*/>.ret;
2448+
let Src1ModDPP = getSrcModDPP_t16<Src1VT, 0 /*IsFake16*/>.ret;
2449+
let Src2ModDPP = getSrcModDPP_t16<Src2VT, 0 /*IsFake16*/>.ret;
24532450

24542451
let DstRC64 = getVALUDstForVT<DstVT, 1 /*IsTrue16*/, 1 /*IsVOP3Encoding*/>.ret;
24552452
let Src0RC64 = getVOP3SrcForVT<Src0VT, 1 /*IsTrue16*/>.ret;
@@ -2465,10 +2462,10 @@ class VOPProfile_Fake16<VOPProfile P> : VOPProfile<P.ArgVT> {
24652462
// Most DstVT are 16-bit, but not all
24662463
let DstRC = getVALUDstForVT_fake16<DstVT>.ret;
24672464
let DstRC64 = getVALUDstForVT<DstVT>.ret;
2468-
let Src1RC32 = RegisterOperand<getVregSrcForVT_t16<Src1VT>.ret>;
2469-
let Src0DPP = getVregSrcForVT_t16<Src0VT>.ret;
2470-
let Src1DPP = getVregSrcForVT_t16<Src1VT>.ret;
2471-
let Src2DPP = getVregSrcForVT_t16<Src2VT>.ret;
2465+
let Src1RC32 = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
2466+
let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
2467+
let Src1DPP = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
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let Src2DPP = getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
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let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret;
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let Src1ModDPP = getSrcModDPP_t16<Src1VT>.ret;
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let Src2ModDPP = getSrcModDPP_t16<Src2VT>.ret;

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