Skip to content

Commit 5aa2acc

Browse files
RKSimonRKSimon
committed
[DAG] SimplifyDemandedVectorElts - remove KnownZero/KnownUndef from DCI helper wrapper
None of the external users actual touch these (they're purely used internally down the recursive call) - its trivial to add another wrapper if anything ever does want to track known elements.
1 parent d919d02 commit 5aa2acc

File tree

4 files changed

+13
-38
lines changed

4 files changed

+13
-38
lines changed

‎llvm/include/llvm/CodeGen/TargetLowering.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3539,7 +3539,6 @@ class TargetLowering : public TargetLoweringBase {
35393539
/// Helper wrapper around SimplifyDemandedVectorElts.
35403540
/// Adds Op back to the worklist upon success.
35413541
bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
3542-
APInt &KnownUndef, APInt &KnownZero,
35433542
DAGCombinerInfo &DCI) const;
35443543

35453544
/// Determine which of the bits specified in Mask are known to be either zero

‎llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2370,13 +2370,12 @@ bool TargetLowering::SimplifyDemandedBits(
23702370

23712371
bool TargetLowering::SimplifyDemandedVectorElts(SDValue Op,
23722372
const APInt &DemandedElts,
2373-
APInt &KnownUndef,
2374-
APInt &KnownZero,
23752373
DAGCombinerInfo &DCI) const {
23762374
SelectionDAG &DAG = DCI.DAG;
23772375
TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23782376
!DCI.isBeforeLegalizeOps());
23792377

2378+
APInt KnownUndef, KnownZero;
23802379
bool Simplified =
23812380
SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero, TLO);
23822381
if (Simplified) {

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 3 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -17060,13 +17060,10 @@ static SDValue PerformVMOVNCombine(SDNode *N,
1706017060
IsTop ? Op1DemandedElts
1706117061
: APInt::getSplat(NumElts, APInt::getHighBitsSet(2, 1));
1706217062

17063-
APInt KnownUndef, KnownZero;
1706417063
const TargetLowering &TLI = DCI.DAG.getTargetLoweringInfo();
17065-
if (TLI.SimplifyDemandedVectorElts(Op0, Op0DemandedElts, KnownUndef,
17066-
KnownZero, DCI))
17064+
if (TLI.SimplifyDemandedVectorElts(Op0, Op0DemandedElts, DCI))
1706717065
return SDValue(N, 0);
17068-
if (TLI.SimplifyDemandedVectorElts(Op1, Op1DemandedElts, KnownUndef,
17069-
KnownZero, DCI))
17066+
if (TLI.SimplifyDemandedVectorElts(Op1, Op1DemandedElts, DCI))
1707017067
return SDValue(N, 0);
1707117068

1707217069
return SDValue();
@@ -17082,10 +17079,8 @@ static SDValue PerformVQMOVNCombine(SDNode *N,
1708217079
APInt::getSplat(NumElts, IsTop ? APInt::getLowBitsSet(2, 1)
1708317080
: APInt::getHighBitsSet(2, 1));
1708417081

17085-
APInt KnownUndef, KnownZero;
1708617082
const TargetLowering &TLI = DCI.DAG.getTargetLoweringInfo();
17087-
if (TLI.SimplifyDemandedVectorElts(Op0, Op0DemandedElts, KnownUndef,
17088-
KnownZero, DCI))
17083+
if (TLI.SimplifyDemandedVectorElts(Op0, Op0DemandedElts, DCI))
1708917084
return SDValue(N, 0);
1709017085
return SDValue();
1709117086
}

‎llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 9 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -40016,10 +40016,8 @@ static SDValue combineShuffle(SDNode *N, SelectionDAG &DAG,
4001640016

4001740017
// Simplify source operands based on shuffle mask.
4001840018
// TODO - merge this into combineX86ShufflesRecursively.
40019-
APInt KnownUndef, KnownZero;
4002040019
APInt DemandedElts = APInt::getAllOnes(VT.getVectorNumElements());
40021-
if (TLI.SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero,
40022-
DCI))
40020+
if (TLI.SimplifyDemandedVectorElts(Op, DemandedElts, DCI))
4002340021
return SDValue(N, 0);
4002440022

4002540023
// Canonicalize SHUFFLE(BINOP(X,Y)) -> BINOP(SHUFFLE(X),SHUFFLE(Y)).
@@ -46034,11 +46032,9 @@ static SDValue combineVectorShiftVar(SDNode *N, SelectionDAG &DAG,
4603446032
EltBits[0].getZExtValue(), DAG);
4603546033
}
4603646034

46037-
APInt KnownUndef, KnownZero;
4603846035
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4603946036
APInt DemandedElts = APInt::getAllOnes(VT.getVectorNumElements());
46040-
if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, KnownUndef,
46041-
KnownZero, DCI))
46037+
if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, DCI))
4604246038
return SDValue(N, 0);
4604346039

4604446040
return SDValue();
@@ -46915,9 +46911,7 @@ static SDValue combineAnd(SDNode *N, SelectionDAG &DAG,
4691546911
DemandedElts.setBit(I);
4691646912
}
4691746913

46918-
APInt KnownUndef, KnownZero;
46919-
return TLI.SimplifyDemandedVectorElts(OtherOp, DemandedElts, KnownUndef,
46920-
KnownZero, DCI) ||
46914+
return TLI.SimplifyDemandedVectorElts(OtherOp, DemandedElts, DCI) ||
4692146915
TLI.SimplifyDemandedBits(OtherOp, DemandedBits, DemandedElts, DCI);
4692246916
};
4692346917
if (SimplifyUndemandedElts(N0, N1) || SimplifyUndemandedElts(N1, N0)) {
@@ -47389,9 +47383,7 @@ static SDValue combineOr(SDNode *N, SelectionDAG &DAG,
4738947383
if (!EltBits[I].isAllOnes())
4739047384
DemandedElts.setBit(I);
4739147385

47392-
APInt KnownUndef, KnownZero;
47393-
return TLI.SimplifyDemandedVectorElts(OtherOp, DemandedElts, KnownUndef,
47394-
KnownZero, DCI);
47386+
return TLI.SimplifyDemandedVectorElts(OtherOp, DemandedElts, DCI);
4739547387
};
4739647388
if (SimplifyUndemandedElts(N0, N1) || SimplifyUndemandedElts(N1, N0)) {
4739747389
if (N->getOpcode() != ISD::DELETED_NODE)
@@ -48531,10 +48523,8 @@ static SDValue combineVEXTRACT_STORE(SDNode *N, SelectionDAG &DAG,
4853148523
unsigned StElts = MemVT.getSizeInBits() / VT.getScalarSizeInBits();
4853248524
APInt DemandedElts = APInt::getLowBitsSet(VT.getVectorNumElements(), StElts);
4853348525

48534-
APInt KnownUndef, KnownZero;
4853548526
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
48536-
if (TLI.SimplifyDemandedVectorElts(StoredVal, DemandedElts, KnownUndef,
48537-
KnownZero, DCI)) {
48527+
if (TLI.SimplifyDemandedVectorElts(StoredVal, DemandedElts, DCI)) {
4853848528
if (N->getOpcode() != ISD::DELETED_NODE)
4853948529
DCI.AddToWorklist(N);
4854048530
return SDValue(N, 0);
@@ -50074,10 +50064,8 @@ static SDValue combineX86INT_TO_FP(SDNode *N, SelectionDAG &DAG,
5007450064
EVT VT = N->getValueType(0);
5007550065
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5007650066

50077-
APInt KnownUndef, KnownZero;
5007850067
APInt DemandedElts = APInt::getAllOnes(VT.getVectorNumElements());
50079-
if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, KnownUndef,
50080-
KnownZero, DCI))
50068+
if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, DCI))
5008150069
return SDValue(N, 0);
5008250070

5008350071
// Convert a full vector load into vzload when not all bits are needed.
@@ -50191,11 +50179,9 @@ static SDValue combineCVTPH2PS(SDNode *N, SelectionDAG &DAG,
5019150179
SDValue Src = N->getOperand(IsStrict ? 1 : 0);
5019250180

5019350181
if (N->getValueType(0) == MVT::v4f32 && Src.getValueType() == MVT::v8i16) {
50194-
APInt KnownUndef, KnownZero;
5019550182
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5019650183
APInt DemandedElts = APInt::getLowBitsSet(8, 4);
50197-
if (TLI.SimplifyDemandedVectorElts(Src, DemandedElts, KnownUndef, KnownZero,
50198-
DCI)) {
50184+
if (TLI.SimplifyDemandedVectorElts(Src, DemandedElts, DCI)) {
5019950185
if (N->getOpcode() != ISD::DELETED_NODE)
5020050186
DCI.AddToWorklist(N);
5020150187
return SDValue(N, 0);
@@ -53476,11 +53462,9 @@ static SDValue combineVPMADD(SDNode *N, SelectionDAG &DAG,
5347653462
ISD::isBuildVectorAllZeros(RHS.getNode()))
5347753463
return DAG.getConstant(0, SDLoc(N), VT);
5347853464

53479-
APInt KnownUndef, KnownZero;
5348053465
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5348153466
APInt DemandedElts = APInt::getAllOnes(VT.getVectorNumElements());
53482-
if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, KnownUndef,
53483-
KnownZero, DCI))
53467+
if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, DCI))
5348453468
return SDValue(N, 0);
5348553469

5348653470
return SDValue();
@@ -53549,11 +53533,9 @@ static SDValue combineKSHIFT(SDNode *N, SelectionDAG &DAG,
5354953533
if (ISD::isBuildVectorAllZeros(N->getOperand(0).getNode()))
5355053534
return DAG.getConstant(0, SDLoc(N), VT);
5355153535

53552-
APInt KnownUndef, KnownZero;
5355353536
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5355453537
APInt DemandedElts = APInt::getAllOnes(VT.getVectorNumElements());
53555-
if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, KnownUndef,
53556-
KnownZero, DCI))
53538+
if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, DCI))
5355753539
return SDValue(N, 0);
5355853540

5355953541
return SDValue();

0 commit comments

Comments
 (0)