We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent bc4fe8a commit 5b18109Copy full SHA for 5b18109
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -566,7 +566,9 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
566
}
567
568
569
- if (!NOutVT.isVector() && InOp.getValueType().isVector()) {
+ // TODO: Handle big endian
570
+ if (!NOutVT.isVector() && InOp.getValueType().isVector() &&
571
+ DAG.getDataLayout().isLittleEndian()) {
572
// Pad the vector operand with undef and cast to a wider integer.
573
EVT EltVT = InOp.getValueType().getVectorElementType();
574
TypeSize EltSize = EltVT.getSizeInBits();
0 commit comments