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[ARM][X86][NFC] Use lambda to avoid duplicate switches in areLoadsFromSameBasePtr (#72376)
Both the Arm and X86 implementations of areLoadsFromSameBasePtr use a switch over the machine opcode, and repeat the same logic for both SDNode operands. We can avoid the duplicated logic (especially lengthy in the X86 case) by just using a lambda. This could obviously be a candidate for moving out to a separate helper function if there were other users, but I've made the minimal change in this patch.
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-206
lines changed

2 files changed

+115
-206
lines changed

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

Lines changed: 24 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -1953,46 +1953,32 @@ bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
19531953
if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
19541954
return false;
19551955

1956-
switch (Load1->getMachineOpcode()) {
1957-
default:
1958-
return false;
1959-
case ARM::LDRi12:
1960-
case ARM::LDRBi12:
1961-
case ARM::LDRD:
1962-
case ARM::LDRH:
1963-
case ARM::LDRSB:
1964-
case ARM::LDRSH:
1965-
case ARM::VLDRD:
1966-
case ARM::VLDRS:
1967-
case ARM::t2LDRi8:
1968-
case ARM::t2LDRBi8:
1969-
case ARM::t2LDRDi8:
1970-
case ARM::t2LDRSHi8:
1971-
case ARM::t2LDRi12:
1972-
case ARM::t2LDRBi12:
1973-
case ARM::t2LDRSHi12:
1974-
break;
1975-
}
1956+
auto IsLoadOpcode = [&](unsigned Opcode) {
1957+
switch (Opcode) {
1958+
default:
1959+
return false;
1960+
case ARM::LDRi12:
1961+
case ARM::LDRBi12:
1962+
case ARM::LDRD:
1963+
case ARM::LDRH:
1964+
case ARM::LDRSB:
1965+
case ARM::LDRSH:
1966+
case ARM::VLDRD:
1967+
case ARM::VLDRS:
1968+
case ARM::t2LDRi8:
1969+
case ARM::t2LDRBi8:
1970+
case ARM::t2LDRDi8:
1971+
case ARM::t2LDRSHi8:
1972+
case ARM::t2LDRi12:
1973+
case ARM::t2LDRBi12:
1974+
case ARM::t2LDRSHi12:
1975+
return true;
1976+
}
1977+
};
19761978

1977-
switch (Load2->getMachineOpcode()) {
1978-
default:
1979+
if (!IsLoadOpcode(Load1->getMachineOpcode()) ||
1980+
!IsLoadOpcode(Load2->getMachineOpcode()))
19791981
return false;
1980-
case ARM::LDRi12:
1981-
case ARM::LDRBi12:
1982-
case ARM::LDRD:
1983-
case ARM::LDRH:
1984-
case ARM::LDRSB:
1985-
case ARM::LDRSH:
1986-
case ARM::VLDRD:
1987-
case ARM::VLDRS:
1988-
case ARM::t2LDRi8:
1989-
case ARM::t2LDRBi8:
1990-
case ARM::t2LDRSHi8:
1991-
case ARM::t2LDRi12:
1992-
case ARM::t2LDRBi12:
1993-
case ARM::t2LDRSHi12:
1994-
break;
1995-
}
19961982

19971983
// Check if base addresses and chain operands match.
19981984
if (Load1->getOperand(0) != Load2->getOperand(0) ||

‎llvm/lib/Target/X86/X86InstrInfo.cpp

Lines changed: 91 additions & 168 deletions
Original file line numberDiff line numberDiff line change
@@ -7636,174 +7636,97 @@ X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
76367636
int64_t &Offset1, int64_t &Offset2) const {
76377637
if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
76387638
return false;
7639-
unsigned Opc1 = Load1->getMachineOpcode();
7640-
unsigned Opc2 = Load2->getMachineOpcode();
7641-
switch (Opc1) {
7642-
default: return false;
7643-
case X86::MOV8rm:
7644-
case X86::MOV16rm:
7645-
case X86::MOV32rm:
7646-
case X86::MOV64rm:
7647-
case X86::LD_Fp32m:
7648-
case X86::LD_Fp64m:
7649-
case X86::LD_Fp80m:
7650-
case X86::MOVSSrm:
7651-
case X86::MOVSSrm_alt:
7652-
case X86::MOVSDrm:
7653-
case X86::MOVSDrm_alt:
7654-
case X86::MMX_MOVD64rm:
7655-
case X86::MMX_MOVQ64rm:
7656-
case X86::MOVAPSrm:
7657-
case X86::MOVUPSrm:
7658-
case X86::MOVAPDrm:
7659-
case X86::MOVUPDrm:
7660-
case X86::MOVDQArm:
7661-
case X86::MOVDQUrm:
7662-
// AVX load instructions
7663-
case X86::VMOVSSrm:
7664-
case X86::VMOVSSrm_alt:
7665-
case X86::VMOVSDrm:
7666-
case X86::VMOVSDrm_alt:
7667-
case X86::VMOVAPSrm:
7668-
case X86::VMOVUPSrm:
7669-
case X86::VMOVAPDrm:
7670-
case X86::VMOVUPDrm:
7671-
case X86::VMOVDQArm:
7672-
case X86::VMOVDQUrm:
7673-
case X86::VMOVAPSYrm:
7674-
case X86::VMOVUPSYrm:
7675-
case X86::VMOVAPDYrm:
7676-
case X86::VMOVUPDYrm:
7677-
case X86::VMOVDQAYrm:
7678-
case X86::VMOVDQUYrm:
7679-
// AVX512 load instructions
7680-
case X86::VMOVSSZrm:
7681-
case X86::VMOVSSZrm_alt:
7682-
case X86::VMOVSDZrm:
7683-
case X86::VMOVSDZrm_alt:
7684-
case X86::VMOVAPSZ128rm:
7685-
case X86::VMOVUPSZ128rm:
7686-
case X86::VMOVAPSZ128rm_NOVLX:
7687-
case X86::VMOVUPSZ128rm_NOVLX:
7688-
case X86::VMOVAPDZ128rm:
7689-
case X86::VMOVUPDZ128rm:
7690-
case X86::VMOVDQU8Z128rm:
7691-
case X86::VMOVDQU16Z128rm:
7692-
case X86::VMOVDQA32Z128rm:
7693-
case X86::VMOVDQU32Z128rm:
7694-
case X86::VMOVDQA64Z128rm:
7695-
case X86::VMOVDQU64Z128rm:
7696-
case X86::VMOVAPSZ256rm:
7697-
case X86::VMOVUPSZ256rm:
7698-
case X86::VMOVAPSZ256rm_NOVLX:
7699-
case X86::VMOVUPSZ256rm_NOVLX:
7700-
case X86::VMOVAPDZ256rm:
7701-
case X86::VMOVUPDZ256rm:
7702-
case X86::VMOVDQU8Z256rm:
7703-
case X86::VMOVDQU16Z256rm:
7704-
case X86::VMOVDQA32Z256rm:
7705-
case X86::VMOVDQU32Z256rm:
7706-
case X86::VMOVDQA64Z256rm:
7707-
case X86::VMOVDQU64Z256rm:
7708-
case X86::VMOVAPSZrm:
7709-
case X86::VMOVUPSZrm:
7710-
case X86::VMOVAPDZrm:
7711-
case X86::VMOVUPDZrm:
7712-
case X86::VMOVDQU8Zrm:
7713-
case X86::VMOVDQU16Zrm:
7714-
case X86::VMOVDQA32Zrm:
7715-
case X86::VMOVDQU32Zrm:
7716-
case X86::VMOVDQA64Zrm:
7717-
case X86::VMOVDQU64Zrm:
7718-
case X86::KMOVBkm:
7719-
case X86::KMOVWkm:
7720-
case X86::KMOVDkm:
7721-
case X86::KMOVQkm:
7722-
break;
7723-
}
7724-
switch (Opc2) {
7725-
default: return false;
7726-
case X86::MOV8rm:
7727-
case X86::MOV16rm:
7728-
case X86::MOV32rm:
7729-
case X86::MOV64rm:
7730-
case X86::LD_Fp32m:
7731-
case X86::LD_Fp64m:
7732-
case X86::LD_Fp80m:
7733-
case X86::MOVSSrm:
7734-
case X86::MOVSSrm_alt:
7735-
case X86::MOVSDrm:
7736-
case X86::MOVSDrm_alt:
7737-
case X86::MMX_MOVD64rm:
7738-
case X86::MMX_MOVQ64rm:
7739-
case X86::MOVAPSrm:
7740-
case X86::MOVUPSrm:
7741-
case X86::MOVAPDrm:
7742-
case X86::MOVUPDrm:
7743-
case X86::MOVDQArm:
7744-
case X86::MOVDQUrm:
7745-
// AVX load instructions
7746-
case X86::VMOVSSrm:
7747-
case X86::VMOVSSrm_alt:
7748-
case X86::VMOVSDrm:
7749-
case X86::VMOVSDrm_alt:
7750-
case X86::VMOVAPSrm:
7751-
case X86::VMOVUPSrm:
7752-
case X86::VMOVAPDrm:
7753-
case X86::VMOVUPDrm:
7754-
case X86::VMOVDQArm:
7755-
case X86::VMOVDQUrm:
7756-
case X86::VMOVAPSYrm:
7757-
case X86::VMOVUPSYrm:
7758-
case X86::VMOVAPDYrm:
7759-
case X86::VMOVUPDYrm:
7760-
case X86::VMOVDQAYrm:
7761-
case X86::VMOVDQUYrm:
7762-
// AVX512 load instructions
7763-
case X86::VMOVSSZrm:
7764-
case X86::VMOVSSZrm_alt:
7765-
case X86::VMOVSDZrm:
7766-
case X86::VMOVSDZrm_alt:
7767-
case X86::VMOVAPSZ128rm:
7768-
case X86::VMOVUPSZ128rm:
7769-
case X86::VMOVAPSZ128rm_NOVLX:
7770-
case X86::VMOVUPSZ128rm_NOVLX:
7771-
case X86::VMOVAPDZ128rm:
7772-
case X86::VMOVUPDZ128rm:
7773-
case X86::VMOVDQU8Z128rm:
7774-
case X86::VMOVDQU16Z128rm:
7775-
case X86::VMOVDQA32Z128rm:
7776-
case X86::VMOVDQU32Z128rm:
7777-
case X86::VMOVDQA64Z128rm:
7778-
case X86::VMOVDQU64Z128rm:
7779-
case X86::VMOVAPSZ256rm:
7780-
case X86::VMOVUPSZ256rm:
7781-
case X86::VMOVAPSZ256rm_NOVLX:
7782-
case X86::VMOVUPSZ256rm_NOVLX:
7783-
case X86::VMOVAPDZ256rm:
7784-
case X86::VMOVUPDZ256rm:
7785-
case X86::VMOVDQU8Z256rm:
7786-
case X86::VMOVDQU16Z256rm:
7787-
case X86::VMOVDQA32Z256rm:
7788-
case X86::VMOVDQU32Z256rm:
7789-
case X86::VMOVDQA64Z256rm:
7790-
case X86::VMOVDQU64Z256rm:
7791-
case X86::VMOVAPSZrm:
7792-
case X86::VMOVUPSZrm:
7793-
case X86::VMOVAPDZrm:
7794-
case X86::VMOVUPDZrm:
7795-
case X86::VMOVDQU8Zrm:
7796-
case X86::VMOVDQU16Zrm:
7797-
case X86::VMOVDQA32Zrm:
7798-
case X86::VMOVDQU32Zrm:
7799-
case X86::VMOVDQA64Zrm:
7800-
case X86::VMOVDQU64Zrm:
7801-
case X86::KMOVBkm:
7802-
case X86::KMOVWkm:
7803-
case X86::KMOVDkm:
7804-
case X86::KMOVQkm:
7805-
break;
7806-
}
7639+
7640+
auto IsLoadOpcode = [&](unsigned Opcode) {
7641+
switch (Opcode) {
7642+
default:
7643+
return false;
7644+
case X86::MOV8rm:
7645+
case X86::MOV16rm:
7646+
case X86::MOV32rm:
7647+
case X86::MOV64rm:
7648+
case X86::LD_Fp32m:
7649+
case X86::LD_Fp64m:
7650+
case X86::LD_Fp80m:
7651+
case X86::MOVSSrm:
7652+
case X86::MOVSSrm_alt:
7653+
case X86::MOVSDrm:
7654+
case X86::MOVSDrm_alt:
7655+
case X86::MMX_MOVD64rm:
7656+
case X86::MMX_MOVQ64rm:
7657+
case X86::MOVAPSrm:
7658+
case X86::MOVUPSrm:
7659+
case X86::MOVAPDrm:
7660+
case X86::MOVUPDrm:
7661+
case X86::MOVDQArm:
7662+
case X86::MOVDQUrm:
7663+
// AVX load instructions
7664+
case X86::VMOVSSrm:
7665+
case X86::VMOVSSrm_alt:
7666+
case X86::VMOVSDrm:
7667+
case X86::VMOVSDrm_alt:
7668+
case X86::VMOVAPSrm:
7669+
case X86::VMOVUPSrm:
7670+
case X86::VMOVAPDrm:
7671+
case X86::VMOVUPDrm:
7672+
case X86::VMOVDQArm:
7673+
case X86::VMOVDQUrm:
7674+
case X86::VMOVAPSYrm:
7675+
case X86::VMOVUPSYrm:
7676+
case X86::VMOVAPDYrm:
7677+
case X86::VMOVUPDYrm:
7678+
case X86::VMOVDQAYrm:
7679+
case X86::VMOVDQUYrm:
7680+
// AVX512 load instructions
7681+
case X86::VMOVSSZrm:
7682+
case X86::VMOVSSZrm_alt:
7683+
case X86::VMOVSDZrm:
7684+
case X86::VMOVSDZrm_alt:
7685+
case X86::VMOVAPSZ128rm:
7686+
case X86::VMOVUPSZ128rm:
7687+
case X86::VMOVAPSZ128rm_NOVLX:
7688+
case X86::VMOVUPSZ128rm_NOVLX:
7689+
case X86::VMOVAPDZ128rm:
7690+
case X86::VMOVUPDZ128rm:
7691+
case X86::VMOVDQU8Z128rm:
7692+
case X86::VMOVDQU16Z128rm:
7693+
case X86::VMOVDQA32Z128rm:
7694+
case X86::VMOVDQU32Z128rm:
7695+
case X86::VMOVDQA64Z128rm:
7696+
case X86::VMOVDQU64Z128rm:
7697+
case X86::VMOVAPSZ256rm:
7698+
case X86::VMOVUPSZ256rm:
7699+
case X86::VMOVAPSZ256rm_NOVLX:
7700+
case X86::VMOVUPSZ256rm_NOVLX:
7701+
case X86::VMOVAPDZ256rm:
7702+
case X86::VMOVUPDZ256rm:
7703+
case X86::VMOVDQU8Z256rm:
7704+
case X86::VMOVDQU16Z256rm:
7705+
case X86::VMOVDQA32Z256rm:
7706+
case X86::VMOVDQU32Z256rm:
7707+
case X86::VMOVDQA64Z256rm:
7708+
case X86::VMOVDQU64Z256rm:
7709+
case X86::VMOVAPSZrm:
7710+
case X86::VMOVUPSZrm:
7711+
case X86::VMOVAPDZrm:
7712+
case X86::VMOVUPDZrm:
7713+
case X86::VMOVDQU8Zrm:
7714+
case X86::VMOVDQU16Zrm:
7715+
case X86::VMOVDQA32Zrm:
7716+
case X86::VMOVDQU32Zrm:
7717+
case X86::VMOVDQA64Zrm:
7718+
case X86::VMOVDQU64Zrm:
7719+
case X86::KMOVBkm:
7720+
case X86::KMOVWkm:
7721+
case X86::KMOVDkm:
7722+
case X86::KMOVQkm:
7723+
return true;
7724+
}
7725+
};
7726+
7727+
if (!IsLoadOpcode(Load1->getMachineOpcode()) ||
7728+
!IsLoadOpcode(Load2->getMachineOpcode()))
7729+
return false;
78077730

78087731
// Lambda to check if both the loads have the same value for an operand index.
78097732
auto HasSameOp = [&](int I) {

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