Skip to content

Commit 5b8fbcc

Browse files
artagnonartagnon
committed
ValueTracking: pre-commit tests for Div/Rem recurrence
1 parent 4de7026 commit 5b8fbcc

File tree

1 file changed

+230
-0
lines changed

1 file changed

+230
-0
lines changed

‎llvm/test/Analysis/ValueTracking/recurrence-knownbits.ll

Lines changed: 230 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -81,6 +81,236 @@ exit:
8181
ret i64 %res
8282
}
8383

84+
define i64 @test_udiv(i1 %c) {
85+
; CHECK-LABEL: @test_udiv(
86+
; CHECK-NEXT: entry:
87+
; CHECK-NEXT: br label [[LOOP:%.*]]
88+
; CHECK: loop:
89+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 9, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
90+
; CHECK-NEXT: [[IV_NEXT]] = udiv i64 [[IV]], 3
91+
; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
92+
; CHECK: exit:
93+
; CHECK-NEXT: [[RES:%.*]] = and i64 [[IV]], 16
94+
; CHECK-NEXT: ret i64 [[RES]]
95+
;
96+
entry:
97+
br label %loop
98+
loop:
99+
%iv = phi i64 [9, %entry], [%iv.next, %loop]
100+
%iv.next = udiv i64 %iv, 3
101+
br i1 %c, label %exit, label %loop
102+
exit:
103+
%res = and i64 %iv, 16
104+
ret i64 %res
105+
}
106+
107+
define i64 @test_sdiv(i1 %c) {
108+
; CHECK-LABEL: @test_sdiv(
109+
; CHECK-NEXT: entry:
110+
; CHECK-NEXT: br label [[LOOP:%.*]]
111+
; CHECK: loop:
112+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ -9, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
113+
; CHECK-NEXT: [[IV_NEXT]] = sdiv i64 [[IV]], -3
114+
; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
115+
; CHECK: exit:
116+
; CHECK-NEXT: [[RES:%.*]] = and i64 [[IV]], 16
117+
; CHECK-NEXT: ret i64 [[RES]]
118+
;
119+
entry:
120+
br label %loop
121+
loop:
122+
%iv = phi i64 [-9, %entry], [%iv.next, %loop]
123+
%iv.next = sdiv i64 %iv, -3
124+
br i1 %c, label %exit, label %loop
125+
exit:
126+
%res = and i64 %iv, 16
127+
ret i64 %res
128+
}
129+
130+
define i64 @test_sdiv2(i1 %c) {
131+
; CHECK-LABEL: @test_sdiv2(
132+
; CHECK-NEXT: entry:
133+
; CHECK-NEXT: br label [[LOOP:%.*]]
134+
; CHECK: loop:
135+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ -9, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
136+
; CHECK-NEXT: [[IV_NEXT]] = sdiv i64 [[IV]], 3
137+
; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
138+
; CHECK: exit:
139+
; CHECK-NEXT: [[RES:%.*]] = and i64 [[IV]], 16
140+
; CHECK-NEXT: ret i64 [[RES]]
141+
;
142+
entry:
143+
br label %loop
144+
loop:
145+
%iv = phi i64 [-9, %entry], [%iv.next, %loop]
146+
%iv.next = sdiv i64 %iv, 3
147+
br i1 %c, label %exit, label %loop
148+
exit:
149+
%res = and i64 %iv, 16
150+
ret i64 %res
151+
}
152+
153+
define i64 @test_sdiv3(i1 %c) {
154+
; CHECK-LABEL: @test_sdiv3(
155+
; CHECK-NEXT: entry:
156+
; CHECK-NEXT: br label [[LOOP:%.*]]
157+
; CHECK: loop:
158+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 9, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
159+
; CHECK-NEXT: [[IV_NEXT]] = sdiv i64 [[IV]], -3
160+
; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
161+
; CHECK: exit:
162+
; CHECK-NEXT: [[RES:%.*]] = and i64 [[IV]], -16
163+
; CHECK-NEXT: ret i64 [[RES]]
164+
;
165+
entry:
166+
br label %loop
167+
loop:
168+
%iv = phi i64 [9, %entry], [%iv.next, %loop]
169+
%iv.next = sdiv i64 %iv, -3
170+
br i1 %c, label %exit, label %loop
171+
exit:
172+
%res = and i64 %iv, -16
173+
ret i64 %res
174+
}
175+
176+
define i64 @test_urem(i1 %c) {
177+
; CHECK-LABEL: @test_urem(
178+
; CHECK-NEXT: entry:
179+
; CHECK-NEXT: br label [[LOOP:%.*]]
180+
; CHECK: loop:
181+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 3, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
182+
; CHECK-NEXT: [[IV_NEXT]] = urem i64 9, [[IV]]
183+
; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
184+
; CHECK: exit:
185+
; CHECK-NEXT: [[RES:%.*]] = and i64 [[IV]], 4
186+
; CHECK-NEXT: ret i64 [[RES]]
187+
;
188+
entry:
189+
br label %loop
190+
loop:
191+
%iv = phi i64 [3, %entry], [%iv.next, %loop]
192+
%iv.next = urem i64 9, %iv
193+
br i1 %c, label %exit, label %loop
194+
exit:
195+
%res = and i64 %iv, 4
196+
ret i64 %res
197+
}
198+
199+
define i64 @test_srem(i1 %c) {
200+
; CHECK-LABEL: @test_srem(
201+
; CHECK-NEXT: entry:
202+
; CHECK-NEXT: br label [[LOOP:%.*]]
203+
; CHECK: loop:
204+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ -9, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
205+
; CHECK-NEXT: [[IV_NEXT]] = srem i64 [[IV]], 3
206+
; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
207+
; CHECK: exit:
208+
; CHECK-NEXT: [[RES:%.*]] = and i64 [[IV]], 16
209+
; CHECK-NEXT: ret i64 [[RES]]
210+
;
211+
entry:
212+
br label %loop
213+
loop:
214+
%iv = phi i64 [-9, %entry], [%iv.next, %loop]
215+
%iv.next = srem i64 %iv, -3
216+
br i1 %c, label %exit, label %loop
217+
exit:
218+
%res = and i64 %iv, 16
219+
ret i64 %res
220+
}
221+
222+
define i64 @test_srem2(i1 %c) {
223+
; CHECK-LABEL: @test_srem2(
224+
; CHECK-NEXT: entry:
225+
; CHECK-NEXT: br label [[LOOP:%.*]]
226+
; CHECK: loop:
227+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ -9, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
228+
; CHECK-NEXT: [[IV_NEXT]] = srem i64 [[IV]], 3
229+
; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
230+
; CHECK: exit:
231+
; CHECK-NEXT: [[RES:%.*]] = and i64 [[IV]], 16
232+
; CHECK-NEXT: ret i64 [[RES]]
233+
;
234+
entry:
235+
br label %loop
236+
loop:
237+
%iv = phi i64 [-9, %entry], [%iv.next, %loop]
238+
%iv.next = srem i64 %iv, 3
239+
br i1 %c, label %exit, label %loop
240+
exit:
241+
%res = and i64 %iv, 16
242+
ret i64 %res
243+
}
244+
245+
define i64 @test_srem2_flipped(i1 %c) {
246+
; CHECK-LABEL: @test_srem2_flipped(
247+
; CHECK-NEXT: entry:
248+
; CHECK-NEXT: br label [[LOOP:%.*]]
249+
; CHECK: loop:
250+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 3, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
251+
; CHECK-NEXT: [[IV_NEXT]] = srem i64 -9, [[IV]]
252+
; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
253+
; CHECK: exit:
254+
; CHECK-NEXT: [[RES:%.*]] = and i64 [[IV]], 4
255+
; CHECK-NEXT: ret i64 [[RES]]
256+
;
257+
entry:
258+
br label %loop
259+
loop:
260+
%iv = phi i64 [3, %entry], [%iv.next, %loop]
261+
%iv.next = srem i64 -9, %iv
262+
br i1 %c, label %exit, label %loop
263+
exit:
264+
%res = and i64 %iv, 4
265+
ret i64 %res
266+
}
267+
268+
define i64 @test_srem3(i1 %c) {
269+
; CHECK-LABEL: @test_srem3(
270+
; CHECK-NEXT: entry:
271+
; CHECK-NEXT: br label [[LOOP:%.*]]
272+
; CHECK: loop:
273+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 9, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
274+
; CHECK-NEXT: [[IV_NEXT]] = srem i64 [[IV]], 3
275+
; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
276+
; CHECK: exit:
277+
; CHECK-NEXT: [[RES:%.*]] = and i64 [[IV]], -16
278+
; CHECK-NEXT: ret i64 [[RES]]
279+
;
280+
entry:
281+
br label %loop
282+
loop:
283+
%iv = phi i64 [9, %entry], [%iv.next, %loop]
284+
%iv.next = srem i64 %iv, -3
285+
br i1 %c, label %exit, label %loop
286+
exit:
287+
%res = and i64 %iv, -16
288+
ret i64 %res
289+
}
290+
291+
define i64 @test_srem3_flipped(i1 %c) {
292+
; CHECK-LABEL: @test_srem3_flipped(
293+
; CHECK-NEXT: entry:
294+
; CHECK-NEXT: br label [[LOOP:%.*]]
295+
; CHECK: loop:
296+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ -3, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
297+
; CHECK-NEXT: [[IV_NEXT]] = srem i64 9, [[IV]]
298+
; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
299+
; CHECK: exit:
300+
; CHECK-NEXT: [[RES:%.*]] = and i64 [[IV]], -4
301+
; CHECK-NEXT: ret i64 [[RES]]
302+
;
303+
entry:
304+
br label %loop
305+
loop:
306+
%iv = phi i64 [-3, %entry], [%iv.next, %loop]
307+
%iv.next = srem i64 9, %iv
308+
br i1 %c, label %exit, label %loop
309+
exit:
310+
%res = and i64 %iv, -4
311+
ret i64 %res
312+
}
313+
84314
define i64 @test_and(i1 %c) {
85315
; CHECK-LABEL: @test_and(
86316
; CHECK-NEXT: entry:

0 commit comments

Comments
 (0)