[DAG] getValidShiftAmountRange - move responsibility of the Depth operands to the caller

Author: RKSimon

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

@@ -3050,8 +3050,7 @@ SelectionDAG::getValidShiftAmountRange(SDValue V, const APInt &DemandedElts,
 
   // Use computeKnownBits to find a hidden constant/knownbits (usually type
   // legalized). e.g. Hidden behind multiple bitcasts/build_vector/casts etc.
-  KnownBits KnownAmt =
-      computeKnownBits(V.getOperand(1), DemandedElts, Depth + 1);
+  KnownBits KnownAmt = computeKnownBits(V.getOperand(1), DemandedElts, Depth);
   if (KnownAmt.getMaxValue().ult(BitWidth))
     return ConstantRange::fromKnownBits(KnownAmt, /*IsSigned=*/false);
 
@@ -3585,7 +3584,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
 
     // Minimum shift low bits are known zero.
     if (std::optional<uint64_t> ShMinAmt =
-            getValidMinimumShiftAmount(Op, DemandedElts, Depth))
+            getValidMinimumShiftAmount(Op, DemandedElts, Depth + 1))
       Known.Zero.setLowBits(*ShMinAmt);
     break;
   }
@@ -3597,7 +3596,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
 
     // Minimum shift high bits are known zero.
     if (std::optional<uint64_t> ShMinAmt =
-            getValidMinimumShiftAmount(Op, DemandedElts, Depth))
+            getValidMinimumShiftAmount(Op, DemandedElts, Depth + 1))
       Known.Zero.setHighBits(*ShMinAmt);
     break;
   case ISD::SRA:
@@ -4603,12 +4602,12 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
     Tmp = ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
     // SRA X, C -> adds C sign bits.
     if (std::optional<uint64_t> ShAmt =
-            getValidMinimumShiftAmount(Op, DemandedElts, Depth))
+            getValidMinimumShiftAmount(Op, DemandedElts, Depth + 1))
       Tmp = std::min<uint64_t>(Tmp + *ShAmt, VTBits);
     return Tmp;
   case ISD::SHL:
     if (std::optional<uint64_t> ShAmt =
-            getValidMaximumShiftAmount(Op, DemandedElts, Depth)) {
+            getValidMaximumShiftAmount(Op, DemandedElts, Depth + 1)) {
       // shl destroys sign bits, ensure it doesn't shift out all sign bits.
       Tmp = ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
       if (*ShAmt < Tmp)
@@ -5285,7 +5284,7 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
   case ISD::SRL:
   case ISD::SRA:
     // If the max shift amount isn't in range, then the shift can create poison.
-    return !getValidMaximumShiftAmount(Op, DemandedElts, Depth);
+    return !getValidMaximumShiftAmount(Op, DemandedElts, Depth + 1);
 
   case ISD::SCALAR_TO_VECTOR:
     // Check if we demand any upper (undef) elements.

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

@@ -797,7 +797,7 @@ SDValue TargetLowering::SimplifyMultipleUseDemandedBits(
     // If we are only demanding sign bits then we can use the shift source
     // directly.
     if (std::optional<uint64_t> MaxSA =
-            DAG.getValidMaximumShiftAmount(Op, DemandedElts, Depth)) {
+            DAG.getValidMaximumShiftAmount(Op, DemandedElts, Depth + 1)) {
       SDValue Op0 = Op.getOperand(0);
       unsigned ShAmt = *MaxSA;
       unsigned NumSignBits =
@@ -1737,7 +1737,7 @@ bool TargetLowering::SimplifyDemandedBits(
     EVT ShiftVT = Op1.getValueType();
 
     if (std::optional<uint64_t> KnownSA =
-            TLO.DAG.getValidShiftAmount(Op, DemandedElts, Depth)) {
+            TLO.DAG.getValidShiftAmount(Op, DemandedElts, Depth + 1)) {
       unsigned ShAmt = *KnownSA;
       if (ShAmt == 0)
         return TLO.CombineTo(Op, Op0);
@@ -1749,7 +1749,7 @@ bool TargetLowering::SimplifyDemandedBits(
       if (Op0.getOpcode() == ISD::SRL) {
         if (!DemandedBits.intersects(APInt::getLowBitsSet(BitWidth, ShAmt))) {
           if (std::optional<uint64_t> InnerSA =
-                  TLO.DAG.getValidShiftAmount(Op0, DemandedElts, Depth + 1)) {
+                  TLO.DAG.getValidShiftAmount(Op0, DemandedElts, Depth + 2)) {
             unsigned C1 = *InnerSA;
             unsigned Opc = ISD::SHL;
             int Diff = ShAmt - C1;
@@ -1789,7 +1789,7 @@ bool TargetLowering::SimplifyDemandedBits(
         if (InnerOp.getOpcode() == ISD::SRL && Op0.hasOneUse() &&
             InnerOp.hasOneUse()) {
           if (std::optional<uint64_t> SA2 = TLO.DAG.getValidShiftAmount(
-                  InnerOp, DemandedElts, Depth + 1)) {
+                  InnerOp, DemandedElts, Depth + 2)) {
             unsigned InnerShAmt = *SA2;
             if (InnerShAmt < ShAmt && InnerShAmt < InnerBits &&
                 DemandedBits.getActiveBits() <=
@@ -1918,7 +1918,7 @@ bool TargetLowering::SimplifyDemandedBits(
     // If we are only demanding sign bits then we can use the shift source
     // directly.
     if (std::optional<uint64_t> MaxSA =
-            TLO.DAG.getValidMaximumShiftAmount(Op, DemandedElts, Depth)) {
+            TLO.DAG.getValidMaximumShiftAmount(Op, DemandedElts, Depth + 1)) {
       unsigned ShAmt = *MaxSA;
       unsigned NumSignBits =
           TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1);
@@ -1934,7 +1934,7 @@ bool TargetLowering::SimplifyDemandedBits(
     EVT ShiftVT = Op1.getValueType();
 
     if (std::optional<uint64_t> KnownSA =
-            TLO.DAG.getValidShiftAmount(Op, DemandedElts, Depth)) {
+            TLO.DAG.getValidShiftAmount(Op, DemandedElts, Depth + 1)) {
       unsigned ShAmt = *KnownSA;
       if (ShAmt == 0)
         return TLO.CombineTo(Op, Op0);
@@ -1946,7 +1946,7 @@ bool TargetLowering::SimplifyDemandedBits(
       if (Op0.getOpcode() == ISD::SHL) {
         if (!DemandedBits.intersects(APInt::getHighBitsSet(BitWidth, ShAmt))) {
           if (std::optional<uint64_t> InnerSA =
-                  TLO.DAG.getValidShiftAmount(Op0, DemandedElts, Depth + 1)) {
+                  TLO.DAG.getValidShiftAmount(Op0, DemandedElts, Depth + 2)) {
             unsigned C1 = *InnerSA;
             unsigned Opc = ISD::SRL;
             int Diff = ShAmt - C1;
@@ -2041,7 +2041,7 @@ bool TargetLowering::SimplifyDemandedBits(
       return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1));
 
     if (std::optional<uint64_t> KnownSA =
-            TLO.DAG.getValidShiftAmount(Op, DemandedElts, Depth)) {
+            TLO.DAG.getValidShiftAmount(Op, DemandedElts, Depth + 1)) {
       unsigned ShAmt = *KnownSA;
       if (ShAmt == 0)
         return TLO.CombineTo(Op, Op0);
@@ -2050,7 +2050,7 @@ bool TargetLowering::SimplifyDemandedBits(
       // supports sext_inreg.
       if (Op0.getOpcode() == ISD::SHL) {
         if (std::optional<uint64_t> InnerSA =
-                TLO.DAG.getValidShiftAmount(Op0, DemandedElts, Depth + 1)) {
+                TLO.DAG.getValidShiftAmount(Op0, DemandedElts, Depth + 2)) {
           unsigned LowBits = BitWidth - ShAmt;
           EVT ExtVT = EVT::getIntegerVT(*TLO.DAG.getContext(), LowBits);
           if (VT.isVector())
@@ -2596,7 +2596,7 @@ bool TargetLowering::SimplifyDemandedBits(
 
       if (Src.getNode()->hasOneUse()) {
         std::optional<uint64_t> ShAmtC =
-            TLO.DAG.getValidShiftAmount(Src, DemandedElts, Depth + 1);
+            TLO.DAG.getValidShiftAmount(Src, DemandedElts, Depth + 2);
         if (!ShAmtC || *ShAmtC >= BitWidth)
           break;
         uint64_t ShVal = *ShAmtC;