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[clang][ARM] PACBTI-M assembly support
Introduce assembly support for Armv8.1-M PACBTI extension. This is an optional extension in v8.1-M. There are 10 new system registers and 5 new instructions, all predicated on the feature. The attribute for llvm-mc is called "pacbti". For armclang, an architecture extension also called "pacbti" was created. This patch is part of a series that adds support for the PACBTI-M extension of the Armv8.1-M architecture, as detailed here: https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension The PACBTI-M specification can be found in the Armv8-M Architecture Reference Manual: https://developer.arm.com/documentation/ddi0553/latest The following people contributed to this patch: - Victor Campos - Ties Stuij Reviewed By: labrinea Differential Revision: https://reviews.llvm.org/D112420
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‎clang/test/Driver/armv8.1m.main.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,10 @@
22
// RUN: FileCheck --check-prefix=CHECK-DSP < %t %s
33
// CHECK-DSP: "-target-feature" "+dsp"
44

5+
// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main+pacbti -### %s 2> %t
6+
// RUN: FileCheck --check-prefix=CHECK-PACBTI < %t %s
7+
// CHECK-PACBTI: "-target-feature" "+pacbti"
8+
59
// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main+fp -### %s 2> %t
610
// RUN: FileCheck --check-prefix=CHECK-FP < %t %s
711
// CHECK-FP-DAG: "-target-feature" "+fp-armv8d16sp"

‎llvm/include/llvm/Support/ARMTargetParser.def

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -201,6 +201,7 @@ ARM_ARCH_EXT_NAME("cdecp4", ARM::AEK_CDECP4, "+cdecp4", "-cdecp4")
201201
ARM_ARCH_EXT_NAME("cdecp5", ARM::AEK_CDECP5, "+cdecp5", "-cdecp5")
202202
ARM_ARCH_EXT_NAME("cdecp6", ARM::AEK_CDECP6, "+cdecp6", "-cdecp6")
203203
ARM_ARCH_EXT_NAME("cdecp7", ARM::AEK_CDECP7, "+cdecp7", "-cdecp7")
204+
ARM_ARCH_EXT_NAME("pacbti", ARM::AEK_PACBTI, "+pacbti", "-pacbti")
204205
#undef ARM_ARCH_EXT_NAME
205206

206207
#ifndef ARM_HW_DIV_NAME

‎llvm/include/llvm/Support/ARMTargetParser.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ enum ArchExtKind : uint64_t {
5959
AEK_CDECP5 = 1 << 27,
6060
AEK_CDECP6 = 1 << 28,
6161
AEK_CDECP7 = 1 << 29,
62-
62+
AEK_PACBTI = 1 << 30,
6363
// Unsupported extensions.
6464
AEK_OS = 1ULL << 59,
6565
AEK_IWMMXT = 1ULL << 60,

‎llvm/lib/Target/ARM/ARM.td

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -442,6 +442,10 @@ def FeatureFixCMSE_CVE_2021_35465 : SubtargetFeature<"fix-cmse-cve-2021-35465",
442442
"Mitigate against the cve-2021-35465 "
443443
"security vulnurability">;
444444

445+
def FeaturePACBTI : SubtargetFeature<"pacbti", "HasPACBTI", "true",
446+
"Enable Pointer Authentication and Branch "
447+
"Target Identification">;
448+
445449
//===----------------------------------------------------------------------===//
446450
// ARM architecture class
447451
//

‎llvm/lib/Target/ARM/ARMInstrThumb2.td

Lines changed: 82 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4055,6 +4055,8 @@ def t2HINT : T2I<(outs), (ins imm0_239:$imm), NoItinerary, "hint", ".w\t$imm",
40554055
bits<8> imm;
40564056
let Inst{31-3} = 0b11110011101011111000000000000;
40574057
let Inst{7-0} = imm;
4058+
4059+
let DecoderMethod = "DecodeT2HintSpaceInstruction";
40584060
}
40594061

40604062
def : t2InstAlias<"hint$p $imm", (t2HINT imm0_239:$imm, pred:$p), 0>;
@@ -4075,6 +4077,11 @@ def : t2InstAlias<"esb$p", (t2HINT 16, pred:$p), 0> {
40754077
def : t2InstAlias<"csdb$p.w", (t2HINT 20, pred:$p), 0>;
40764078
def : t2InstAlias<"csdb$p", (t2HINT 20, pred:$p), 1>;
40774079

4080+
def : t2InstAlias<"pacbti$p r12,lr,sp", (t2HINT 13, pred:$p), 1>;
4081+
def : t2InstAlias<"bti$p", (t2HINT 15, pred:$p), 1>;
4082+
def : t2InstAlias<"pac$p r12,lr,sp", (t2HINT 29, pred:$p), 1>;
4083+
def : t2InstAlias<"aut$p r12,lr,sp", (t2HINT 45, pred:$p), 1>;
4084+
40784085
def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt",
40794086
[(int_arm_dbg imm0_15:$opt)]> {
40804087
bits<4> opt;
@@ -5654,3 +5661,78 @@ let Predicates = [HasV8_1MMainline] in {
56545661
def : InstAlias<"cneg\t$Rd, $Rn, $fcond",
56555662
(t2CSNEG rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond)>;
56565663
}
5664+
5665+
5666+
// PACBTI
5667+
let Predicates = [IsThumb2, HasV8_1MMainline, HasPACBTI] in {
5668+
def t2PACG : V8_1MI<(outs rGPR:$Rd),
5669+
(ins pred:$p, GPRnopc:$Rn, GPRnopc:$Rm),
5670+
AddrModeNone, NoItinerary, "pacg${p}", "$Rd, $Rn, $Rm", "", []> {
5671+
bits<4> Rd;
5672+
bits<4> Rn;
5673+
bits<4> Rm;
5674+
let Inst{31-20} = 0b111110110110;
5675+
let Inst{19-16} = Rn;
5676+
let Inst{15-12} = 0b1111;
5677+
let Inst{11-8} = Rd;
5678+
let Inst{7-4} = 0b0000;
5679+
let Inst{3-0} = Rm;
5680+
}
5681+
5682+
let hasSideEffects = 1 in {
5683+
class PACBTIAut<dag iops, string asm, bit b>
5684+
: V8_1MI<(outs), iops,
5685+
AddrModeNone, NoItinerary, asm, "$Ra, $Rn, $Rm", "", []> {
5686+
bits<4> Ra;
5687+
bits<4> Rn;
5688+
bits<4> Rm;
5689+
let Inst{31-20} = 0b111110110101;
5690+
let Inst{19-16} = Rn;
5691+
let Inst{15-12} = Ra;
5692+
let Inst{11-5} = 0b1111000;
5693+
let Inst{4} = b;
5694+
let Inst{3-0} = Rm;
5695+
}
5696+
}
5697+
5698+
def t2AUTG : PACBTIAut<(ins pred:$p, GPRnosp:$Ra, GPRnopc:$Rn, GPRnopc:$Rm),
5699+
"autg${p}", 0>;
5700+
5701+
let isBranch = 1, isTerminator = 1, isIndirectBranch = 1 in {
5702+
def t2BXAUT : PACBTIAut<(ins pred:$p, GPRnosp:$Ra, rGPR:$Rn, GPRnopc:$Rm),
5703+
"bxaut${p}", 1>;
5704+
}
5705+
}
5706+
5707+
5708+
class PACBTIHintSpaceInst<string asm, string ops, bits<8> imm>
5709+
: V8_1MI<(outs), (ins), AddrModeNone, NoItinerary, asm, ops, "", []> {
5710+
let Inst{31-8} = 0b111100111010111110000000;
5711+
let Inst{7-0} = imm;
5712+
5713+
let Unpredictable{19-16} = 0b1111;
5714+
let Unpredictable{13-11} = 0b101;
5715+
5716+
let DecoderMethod = "DecodeT2HintSpaceInstruction";
5717+
}
5718+
5719+
class PACBTIHintSpaceNoOpsInst<string asm, bits<8> imm>
5720+
: PACBTIHintSpaceInst<asm, "", imm>;
5721+
5722+
class PACBTIHintSpaceDefInst<string asm, bits<8> imm>
5723+
: PACBTIHintSpaceInst<asm, "r12, lr, sp", imm> {
5724+
let Defs = [R12];
5725+
let Uses = [LR, SP];
5726+
}
5727+
5728+
class PACBTIHintSpaceUseInst<string asm, bits<8> imm>
5729+
: PACBTIHintSpaceInst<asm, "r12, lr, sp", imm> {
5730+
let Uses = [R12, LR, SP];
5731+
}
5732+
5733+
def t2PAC : PACBTIHintSpaceDefInst<"pac", 0b00011101>;
5734+
def t2PACBTI : PACBTIHintSpaceDefInst<"pacbti", 0b00001101>;
5735+
def t2BTI : PACBTIHintSpaceNoOpsInst<"bti", 0b00001111>;
5736+
def t2AUT : PACBTIHintSpaceUseInst<"aut", 0b00101101> {
5737+
let hasSideEffects = 1;
5738+
}

‎llvm/lib/Target/ARM/ARMPredicates.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -107,6 +107,8 @@ def HasRAS : Predicate<"Subtarget->hasRAS()">,
107107
AssemblerPredicate<(all_of FeatureRAS), "ras">;
108108
def HasLOB : Predicate<"Subtarget->hasLOB()">,
109109
AssemblerPredicate<(all_of FeatureLOB), "lob">;
110+
def HasPACBTI : Predicate<"Subtarget->hasPACBTI()">,
111+
AssemblerPredicate<(all_of FeaturePACBTI), "pacbti">;
110112
def HasFP16 : Predicate<"Subtarget->hasFP16()">,
111113
AssemblerPredicate<(all_of FeatureFP16),"half-float conversions">;
112114
def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">,

‎llvm/lib/Target/ARM/ARMRegisterInfo.td

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -277,6 +277,16 @@ def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), APSR_NZCV)
277277
let DiagnosticString = "operand must be a register in range [r0, r14] or apsr_nzcv";
278278
}
279279

280+
// GPRs without the SP register. Used for BXAUT and AUTG
281+
def GPRnosp : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), LR, PC)> {
282+
let AltOrders = [(add LR, GPRnosp), (trunc GPRnosp, 8),
283+
(add (trunc GPRnosp, 8), R12, LR, (shl GPRnosp, 8))];
284+
let AltOrderSelect = [{
285+
return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF);
286+
}];
287+
let DiagnosticString = "operand must be a register in range [r0, r12] or LR or PC";
288+
}
289+
280290
// GPRs without the PC and SP registers but with APSR. Used by CLRM instruction.
281291
def GPRwithAPSRnosp : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), LR, APSR)> {
282292
let isAllocatable = 0;

‎llvm/lib/Target/ARM/ARMSubtarget.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -373,6 +373,8 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
373373
/// HasLOB - if true, the processor supports the Low Overhead Branch extension
374374
bool HasLOB = false;
375375

376+
bool HasPACBTI = false;
377+
376378
/// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
377379
/// particularly effective at zeroing a VFP register.
378380
bool HasZeroCycleZeroing = false;
@@ -671,6 +673,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
671673
bool hasCRC() const { return HasCRC; }
672674
bool hasRAS() const { return HasRAS; }
673675
bool hasLOB() const { return HasLOB; }
676+
bool hasPACBTI() const { return HasPACBTI; }
674677
bool hasVirtualization() const { return HasVirtualization; }
675678

676679
bool useNEONForSinglePrecisionFP() const {

‎llvm/lib/Target/ARM/ARMSystemRegister.td

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -106,6 +106,24 @@ def : MClassSysReg<0, 0, 1, 0x894, "control_ns">;
106106
def : MClassSysReg<0, 0, 1, 0x898, "sp_ns">;
107107
}
108108

109+
let Requires = [{ {ARM::FeaturePACBTI} }] in {
110+
def : MClassSysReg<0, 0, 1, 0x820, "pac_key_p_0">;
111+
def : MClassSysReg<0, 0, 1, 0x821, "pac_key_p_1">;
112+
def : MClassSysReg<0, 0, 1, 0x822, "pac_key_p_2">;
113+
def : MClassSysReg<0, 0, 1, 0x823, "pac_key_p_3">;
114+
def : MClassSysReg<0, 0, 1, 0x824, "pac_key_u_0">;
115+
def : MClassSysReg<0, 0, 1, 0x825, "pac_key_u_1">;
116+
def : MClassSysReg<0, 0, 1, 0x826, "pac_key_u_2">;
117+
def : MClassSysReg<0, 0, 1, 0x827, "pac_key_u_3">;
118+
def : MClassSysReg<0, 0, 1, 0x8a0, "pac_key_p_0_ns">;
119+
def : MClassSysReg<0, 0, 1, 0x8a1, "pac_key_p_1_ns">;
120+
def : MClassSysReg<0, 0, 1, 0x8a2, "pac_key_p_2_ns">;
121+
def : MClassSysReg<0, 0, 1, 0x8a3, "pac_key_p_3_ns">;
122+
def : MClassSysReg<0, 0, 1, 0x8a4, "pac_key_u_0_ns">;
123+
def : MClassSysReg<0, 0, 1, 0x8a5, "pac_key_u_1_ns">;
124+
def : MClassSysReg<0, 0, 1, 0x8a6, "pac_key_u_2_ns">;
125+
def : MClassSysReg<0, 0, 1, 0x8a7, "pac_key_u_3_ns">;
126+
}
109127

110128
// Banked Registers
111129
//

‎llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Lines changed: 11 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -6429,15 +6429,17 @@ StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
64296429
Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
64306430
Mnemonic.startswith("vsel") || Mnemonic == "vins" || Mnemonic == "vmovx" ||
64316431
Mnemonic == "bxns" || Mnemonic == "blxns" ||
6432-
Mnemonic == "vdot" || Mnemonic == "vmmla" ||
6432+
Mnemonic == "vdot" || Mnemonic == "vmmla" ||
64336433
Mnemonic == "vudot" || Mnemonic == "vsdot" ||
64346434
Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
64356435
Mnemonic == "vfmal" || Mnemonic == "vfmsl" ||
6436-
Mnemonic == "wls" || Mnemonic == "le" || Mnemonic == "dls" ||
6437-
Mnemonic == "csel" || Mnemonic == "csinc" ||
6436+
Mnemonic == "wls" || Mnemonic == "le" || Mnemonic == "dls" ||
6437+
Mnemonic == "csel" || Mnemonic == "csinc" ||
64386438
Mnemonic == "csinv" || Mnemonic == "csneg" || Mnemonic == "cinc" ||
6439-
Mnemonic == "cinv" || Mnemonic == "cneg" || Mnemonic == "cset" ||
6440-
Mnemonic == "csetm")
6439+
Mnemonic == "cinv" || Mnemonic == "cneg" || Mnemonic == "cset" ||
6440+
Mnemonic == "csetm" ||
6441+
Mnemonic == "aut" || Mnemonic == "pac" || Mnemonic == "pacbti" ||
6442+
Mnemonic == "bti")
64416443
return Mnemonic;
64426444

64436445
// First, split out any predication code. Ignore mnemonics we know aren't
@@ -6581,9 +6583,11 @@ void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic,
65816583
Mnemonic == "csinc" || Mnemonic == "csinv" || Mnemonic == "csneg" ||
65826584
Mnemonic == "cinc" || Mnemonic == "cinv" || Mnemonic == "cneg" ||
65836585
Mnemonic == "cset" || Mnemonic == "csetm" ||
6584-
Mnemonic.startswith("vpt") || Mnemonic.startswith("vpst") ||
65856586
(hasCDE() && MS.isCDEInstr(Mnemonic) &&
65866587
!MS.isITPredicableCDEInstr(Mnemonic)) ||
6588+
Mnemonic.startswith("vpt") || Mnemonic.startswith("vpst") ||
6589+
Mnemonic == "pac" || Mnemonic == "pacbti" || Mnemonic == "aut" ||
6590+
Mnemonic == "bti" ||
65876591
(hasMVE() &&
65886592
(Mnemonic.startswith("vst2") || Mnemonic.startswith("vld2") ||
65896593
Mnemonic.startswith("vst4") || Mnemonic.startswith("vld4") ||
@@ -12272,6 +12276,7 @@ bool ARMAsmParser::enableArchExtFeature(StringRef Name, SMLoc &ExtLoc) {
1227212276
{ARM::FeatureFPARMv8, ARM::FeatureFullFP16}},
1227312277
{ARM::AEK_RAS, {Feature_HasV8Bit}, {ARM::FeatureRAS}},
1227412278
{ARM::AEK_LOB, {Feature_HasV8_1MMainlineBit}, {ARM::FeatureLOB}},
12279+
{ARM::AEK_PACBTI, {Feature_HasV8_1MMainlineBit}, {ARM::FeaturePACBTI}},
1227512280
// FIXME: Unsupported extensions.
1227612281
{ARM::AEK_OS, {}, {}},
1227712282
{ARM::AEK_IWMMXT, {}, {}},

‎llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Lines changed: 65 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -185,8 +185,11 @@ static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
185185
static DecodeStatus
186186
DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
187187
uint64_t Address, const void *Decoder);
188-
static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
189-
unsigned RegNo, uint64_t Address,
188+
static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
189+
uint64_t Address,
190+
const void *Decoder);
191+
static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,
192+
uint64_t Address,
190193
const void *Decoder);
191194
static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
192195
unsigned RegNo, uint64_t Address,
@@ -287,6 +290,9 @@ static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
287290
uint64_t Address, const void *Decoder);
288291
static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
289292
uint64_t Address, const void *Decoder);
293+
static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn,
294+
uint64_t Address,
295+
const void *Decoder);
290296
static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
291297
uint64_t Address, const void *Decoder);
292298
static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
@@ -1172,6 +1178,19 @@ DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
11721178
return S;
11731179
}
11741180

1181+
static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,
1182+
uint64_t Address,
1183+
const void *Decoder) {
1184+
DecodeStatus S = MCDisassembler::Success;
1185+
1186+
if (RegNo == 13)
1187+
S = MCDisassembler::SoftFail;
1188+
1189+
Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1190+
1191+
return S;
1192+
}
1193+
11751194
static DecodeStatus
11761195
DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
11771196
uint64_t Address, const void *Decoder) {
@@ -2441,6 +2460,31 @@ static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
24412460
return S;
24422461
}
24432462

2463+
static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn,
2464+
uint64_t Address,
2465+
const void *Decoder) {
2466+
unsigned imm = fieldFromInstruction(Insn, 0, 8);
2467+
2468+
unsigned Opcode = ARM::t2HINT;
2469+
2470+
if (imm == 0x0D) {
2471+
Opcode = ARM::t2PACBTI;
2472+
} else if (imm == 0x1D) {
2473+
Opcode = ARM::t2PAC;
2474+
} else if (imm == 0x2D) {
2475+
Opcode = ARM::t2AUT;
2476+
} else if (imm == 0x0F) {
2477+
Opcode = ARM::t2BTI;
2478+
}
2479+
2480+
Inst.setOpcode(Opcode);
2481+
if (Opcode == ARM::t2HINT) {
2482+
Inst.addOperand(MCOperand::createImm(imm));
2483+
}
2484+
2485+
return MCDisassembler::Success;
2486+
}
2487+
24442488
static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
24452489
uint64_t Address, const void *Decoder) {
24462490
DecodeStatus S = MCDisassembler::Success;
@@ -4726,6 +4770,25 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
47264770
if (!(FeatureBits[ARM::Feature8MSecExt]))
47274771
return MCDisassembler::Fail;
47284772
break;
4773+
case 0x20: // pac_key_p_0
4774+
case 0x21: // pac_key_p_1
4775+
case 0x22: // pac_key_p_2
4776+
case 0x23: // pac_key_p_3
4777+
case 0x24: // pac_key_u_0
4778+
case 0x25: // pac_key_u_1
4779+
case 0x26: // pac_key_u_2
4780+
case 0x27: // pac_key_u_3
4781+
case 0xa0: // pac_key_p_0_ns
4782+
case 0xa1: // pac_key_p_1_ns
4783+
case 0xa2: // pac_key_p_2_ns
4784+
case 0xa3: // pac_key_p_3_ns
4785+
case 0xa4: // pac_key_u_0_ns
4786+
case 0xa5: // pac_key_u_1_ns
4787+
case 0xa6: // pac_key_u_2_ns
4788+
case 0xa7: // pac_key_u_3_ns
4789+
if (!(FeatureBits[ARM::FeaturePACBTI]))
4790+
return MCDisassembler::Fail;
4791+
break;
47294792
default:
47304793
// Architecturally defined as unpredictable
47314794
S = MCDisassembler::SoftFail;

‎llvm/test/CodeGen/Thumb/high-reg-clobber.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -31,14 +31,14 @@ body: |
3131
; CHECK: tSTRspi [[COPY]], %stack.0, 0, 14 /* CC::al */, $noreg
3232
; CHECK: [[tLDRspi:%[0-9]+]]:tgpr = tLDRspi %stack.0, 0, 14 /* CC::al */, $noreg
3333
; CHECK: [[COPY1:%[0-9]+]]:hgpr = COPY [[tLDRspi]]
34-
; CHECK: INLINEASM &"mov r12, $0", 1 /* sideeffect attdialect */, 1048585 /* reguse:GPRnoip_and_GPRwithAPSR_NZCVnosp */, [[COPY1]], 12 /* clobber */, implicit-def early-clobber $r12
34+
; CHECK: INLINEASM &"mov r12, $0", 1 /* sideeffect attdialect */, 1048585 /* reguse:GPRnoip_and_GPRnopc */, %1, 12 /* clobber */, implicit-def early-clobber $r12
3535
; CHECK: tBX_RET 14 /* CC::al */, $noreg
3636
; FAST-LABEL: name: constraint_h
3737
; FAST: liveins: $r0
3838
; FAST: tSTRspi killed renamable $r0, %stack.0, 0, 14 /* CC::al */, $noreg
3939
; FAST: renamable $r0 = tLDRspi %stack.0, 0, 14 /* CC::al */, $noreg
4040
; FAST: renamable $r8 = COPY killed renamable $r0
41-
; FAST: INLINEASM &"mov r12, $0", 1 /* sideeffect attdialect */, 1048585 /* reguse:GPRnoip_and_GPRwithAPSR_NZCVnosp */, killed renamable $r8, 12 /* clobber */, implicit-def dead early-clobber $r12
41+
; FAST: INLINEASM &"mov r12, $0", 1 /* sideeffect attdialect */, 1048585 /* reguse:GPRnoip_and_GPRnopc */, killed renamable $r8, 12 /* clobber */, implicit-def dead early-clobber $r12
4242
; FAST: tBX_RET 14 /* CC::al */, $noreg
4343
%0:tgpr = COPY $r0
4444
tSTRspi %0, %stack.0, 0, 14 /* CC::al */, $noreg

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