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[X86] LowerShift - use getConstant directly to create vector splat constants. NFC.
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llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -30224,8 +30224,7 @@ static SDValue LowerShift(SDValue Op, const X86Subtarget &Subtarget,
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// another. The construction of this mask will be constant folded.
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// The mask for a logical right shift is nearly identical, the only
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// difference is that the all ones mask is shifted right instead of left.
30227-
SDValue CstFullMask = DAG.getAllOnesConstant(dl, NarrowScalarVT);
30228-
SDValue SplatFullMask = DAG.getSplat(VT, dl, CstFullMask);
30227+
SDValue SplatFullMask = DAG.getAllOnesConstant(dl, VT);
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SDValue Mask = DAG.getNode(LogicalOpc, dl, VT, SplatFullMask, Amt);
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Mask = DAG.getBitcast(WideVT, Mask);
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// Finally, we mask the shifted vector with the SWAR mask.
@@ -30258,9 +30257,8 @@ static SDValue LowerShift(SDValue Op, const X86Subtarget &Subtarget,
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//
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// This is equal to Masked - 2*SignBitMask which will correctly sign
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// extend our result.
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SDValue CstHighBit =
30262-
DAG.getConstant(1ULL << (EltSizeInBits - 1), dl, NarrowScalarVT);
30263-
SDValue SplatHighBit = DAG.getSplat(VT, dl, CstHighBit);
30260+
SDValue SplatHighBit =
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DAG.getConstant(APInt::getSignMask(EltSizeInBits), dl, VT);
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// This does not induce recursion, all operands are constants.
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SDValue SignBitMask = DAG.getNode(LogicalOpc, dl, VT, SplatHighBit, Amt);
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SDValue FlippedSignBit =

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